4 ms·

It can't succeed fast enough. I'm sick of space heaters posing as x86 laptops, and I refuse to voluntarily buy into the Apple ecosystem, even if they do some th

It can't succeed fast enough. I'm sick of space heaters posing as x86 laptops, and I refuse to voluntarily buy into the Apple ecosystem, even if they do some things well. How far away are we from competitive laptop/desktop quality RISC-V chips? It seemed like there were a few extension that everybody was waiting on, but now most of them are complete, and still haven't seen anything of substance.

mixedCase 5y ago
Taking into consideration how long it's taken the ARM industry to get a single decent laptop/desktop processor with the M1 since ARM64 was published. And it's yet to be matched by any other company. Odds are good we're going to be waiting for a while.
- Qem 5y ago
  ARM started at a time when Moore Law still hold strong. It was much harder to catch up. The incumbents can't double their products performance every 18-month anymore. So RISC-V can have a easier time catching up than ARM did, one hopes.
  - mekster 5y ago
    What's the reason the law no longer holds? Physical limitations or Intel just busted with their research?
    - afiori 5y ago
      During a CPU cycle the entire chip needs to stabilize; new voltages come as inputs and some time is required to stabilize the outputs to the correct values, this time cannot be lower that size_of_chip/speed_of_light and it is already quite close, but the chip cannot become much smaller as the transistors are already at an atomic scale. Breakthroughs are now architectural, like if someone figured a way to implement a CPU with half as many transistor we could get a ~30% increase in clock frequency
sprash 5y ago
> space heaters posing as x86 laptops The instruction set has nothing to do with this. Apple has better numbers because it uses the most advanced manufacturing process.
- marcan_42 5y ago
  But it does. x86 is hell to decode in parallel, because it's variable length (and in a complex way), so Intel can't build CPUs that keep a wide pipeline fed with instructions efficiently like Apple can, with the 8-wide decoder in the M1. That's one of the things that makes the M1 special, and how it gets away with lower clocks and power consumption than competing x86 designs.
  - jabl 5y ago
    Current x86 as well as many Arm cores have micro-op caches, so they don't need as wide decoders as a design that doesn't have such a thing, like M1. (That doesn't take away from the fact that M1 is a very impressive design, of course)
  - userbinator 5y ago
    Variable length doesn't matter that much, you just have something that has a wide shifter on the front. And instruction density is important because it saves cache. A single x86 instruction can take the place of several RISC ones, which is why they needed to have it decode so wide. The M1 is almost entirely a process advantage.
    - marcan_42 5y ago
      It's not about a shifter, it's about determining instruction boundaries. With variable-length instructions the next instruction start depends on the previous one, making it an inherently serial process. Working around that to decode in parallel is not easy and gets superlinearly more complex the wider you make the decoder. A fixed instruction size architecture like ARM64 doesn't have to deal with any of that.
kllrnohj 5y ago
> I'm sick of space heaters posing as x86 laptops Then buy AMD? There's choices here, and AMD's laptop CPUs for the last few generations have been very power efficient. See for example today's Anandtech coverage of the latest Zephyrus G14: https://www.anandtech.com/show/17276/amd-ryzen-9-6900hs-rembrandt-benchmark-zen3-plus-scaling/4 https://www.anandtech.com/show/17276/amd-ryzen-9-6900hs-remb... It's nonsensical to think that RISC-V will somehow fix this, since it's a heck of a lot more about execution quality than ISA (fine-grained clocking, power gating, sleep states, etc... as well as just an overall efficient cache & instruction execution design).
GoblinSlayer 5y ago
I run an x86 processor at 50% power and it's less of a heater.

mixedCase 5y ago

Taking into consideration how long it's taken the ARM industry to get a single decent laptop/desktop processor with the M1 since ARM64 was published. And it's yet to be matched by any other company. Odds are good we're going to be waiting for a while.

Qem 5y ago
ARM started at a time when Moore Law still hold strong. It was much harder to catch up. The incumbents can't double their products performance every 18-month anymore. So RISC-V can have a easier time catching up than ARM did, one hopes.
- mekster 5y ago
  What's the reason the law no longer holds? Physical limitations or Intel just busted with their research?
  - afiori 5y ago
    During a CPU cycle the entire chip needs to stabilize; new voltages come as inputs and some time is required to stabilize the outputs to the correct values, this time cannot be lower that size_of_chip/speed_of_light and it is already quite close, but the chip cannot become much smaller as the transistors are already at an atomic scale. Breakthroughs are now architectural, like if someone figured a way to implement a CPU with half as many transistor we could get a ~30% increase in clock frequency

sprash 5y ago

> space heaters posing as x86 laptops The instruction set has nothing to do with this. Apple has better numbers because it uses the most advanced manufacturing process.

marcan_42 5y ago
But it does. x86 is hell to decode in parallel, because it's variable length (and in a complex way), so Intel can't build CPUs that keep a wide pipeline fed with instructions efficiently like Apple can, with the 8-wide decoder in the M1. That's one of the things that makes the M1 special, and how it gets away with lower clocks and power consumption than competing x86 designs.
- jabl 5y ago
  Current x86 as well as many Arm cores have micro-op caches, so they don't need as wide decoders as a design that doesn't have such a thing, like M1. (That doesn't take away from the fact that M1 is a very impressive design, of course)
- userbinator 5y ago
  Variable length doesn't matter that much, you just have something that has a wide shifter on the front. And instruction density is important because it saves cache. A single x86 instruction can take the place of several RISC ones, which is why they needed to have it decode so wide. The M1 is almost entirely a process advantage.
  - marcan_42 5y ago
    It's not about a shifter, it's about determining instruction boundaries. With variable-length instructions the next instruction start depends on the previous one, making it an inherently serial process. Working around that to decode in parallel is not easy and gets superlinearly more complex the wider you make the decoder. A fixed instruction size architecture like ARM64 doesn't have to deal with any of that.

kllrnohj 5y ago

> I'm sick of space heaters posing as x86 laptops Then buy AMD? There's choices here, and AMD's laptop CPUs for the last few generations have been very power efficient. See for example today's Anandtech coverage of the latest Zephyrus G14: https://www.anandtech.com/show/17276/amd-ryzen-9-6900hs-rembrandt-benchmark-zen3-plus-scaling/4 https://www.anandtech.com/show/17276/amd-ryzen-9-6900hs-remb... It's nonsensical to think that RISC-V will somehow fix this, since it's a heck of a lot more about execution quality than ISA (fine-grained clocking, power gating, sleep states, etc... as well as just an overall efficient cache & instruction execution design).

GoblinSlayer 5y ago

I run an x86 processor at 50% power and it's less of a heater.