7 ms·

The machine that saved Moore's Law

70 points by mikro2nd 5y ago

wffurr 5y ago
Reading the development story and just how long they worked on this, with would-be competitors falling by the wayside the whole time, I'm less surprised than I was that Intel missed the boat on this technology. Intel, and apparently almost everyone else other than TSMC, were skeptical this would work. But now that it does, Intel has some catch-up to do to build fabs using these things to match what TSMC is doing with them.
- ballenf 5y ago
  The article mentions Intel is slated to get the first next-gen EUV device ("high-NA EUV"). I wonder how much lead time this buys them from when TSMC gets theirs? Presumably would just be a month or two at most, unless Intel is getting more than just the first. If they can produce 55 of the current generation per year, the next generation would be produced at some order of magnitude slower at first.
  - ksec 5y ago
    You dont buy a few and expect them to work on latest nodes unless you want capacity constrained launch cycle. So it is likely the whole order for that year would go to Intel if they do intend to use it on their 4nm. TSMC has settled on older generation anyway. Their "slightly" delayed 3nm isn't on GAAFET / Nanowire / Ribbonfet or MBCFET. whatever term they decide to use. ( It is getting worse then their "nm" naming ) and not on High-NA EUV either which is scheduled for their 2nm. Sometime in 2025. So the lead time may be around a year and a bit more. And I keep mentioning this everywhere, on HN or Semiwiki and other places. TSMC is a (very) conservative company. Betting on something exotic and not quite ready isn't their thing.
vadiml 5y ago
They say in that article the Intel will produce chips based on 10nm tech in 2025. However Wikipedia says the Apple M1 chips are currently using 5nm tech... How come?
- mnw21cam 5y ago
  Different companies call these technologies different things, but they're fairly divorced from the actual minimum feature size these days. Your advertised feature size is a marketing term, so it's going to be gamed to some extent.
- detaro 5y ago
  There's lots of variation in how companies define their nodes and not really connected to any measurement anymore. I.e. if a company speaks about it's "10nm node" that doesn't mean there is a physical thing 10nm in size (and e.g. Intels 10nm node is often considered to be equivalent to Samsungs 7nm node) - it's better to think of it as a version number in a way. As such, talking about these things gets confusing quickly, and the article also doesn't clarify what exactly it means when it says "10nm in size".
pmlnr 5y ago
"Law" my *ss. At least call it Moore's Belief but rather just forget about it.
- martin_balsam 5y ago
  The number of people who believe that Moore’s Law is dead doubles every 18 months -Jim Keller
  - 1cvmask 5y ago
    That should be Keller’s law
  - ksec 5y ago
    Except Jim Keller refers Moore’s Law to transistor improvement and not doubling of anything, whether that is transistor or performance. We broke the 2x graph for some time already. But that doesn't mean we are not getting 1.7x.
- Melkman 5y ago
  A silicon atom is about 111pm. So 90 atoms is 10nm. What is the minimum size of a feature in atoms before running in to problems with physics?
  - rini17 5y ago
    Oh, they ran into problems with physics long ago. And so far solved them.
  - marcosdumay 5y ago
    > What is the minimum size of a feature in atoms before running in to problems with physics? About 10nm. High-end chips have been there for ages now. Fighting those problems takes quite a bit of creativity.
  - brennanpeterson 5y ago
    As a rule of thumb, about 10 unit cells (5nm). There are some exceptions, but this is a useful number. That means that practically, the smallest conceivable metal pitch is 10nm, the smallest gate is 20. From 5nm, it implies a factor of 10 is left, or about 3-4 nodes.i expect lower scaled nodes at larger delays, but another 15-20 years.
causi 5y ago
saved moore's law When did that happen? Last I checked even Intel's new hotness was struggling to double the IPC of my ancient Haswell.
- alecco 5y ago
  Moore's Law is doubling transistors per area, not IPC, not Mhz, nor bandwidth.
  - gameswithgo 5y ago
    right, which also hasn’t quite been happening lately but the term has changed in popular use to mean something more like “still getting smaller every few years”
  - marcosdumay 5y ago
    Moore's Law is doubling the transistors on the most economical package. EUV would have to be cheap to keep Moore's Law alive.
  - deleted 5y ago
    [deleted]
- api 5y ago
  Everyone knew Moore's law was going to be a sigmoid curve, otherwise we'd be getting transistors smaller than atoms which is impossible. Today the term is used as vernacular for "well we are still getting smaller." Nobody knows what the last process node for conventional flat semiconductors will be, but recent speculation is around 1.5nm. Small embedded and low performance chips may have already topped out in a cost/benefit sense. There's no benefit to a 5nm process microcontroller for a coffee maker. The really small nodes may stay reserved for high performance or ultra low power chips. After we really do hit the top of the sigmoid it doesn't mean computers getting more powerful is over. It just means we would have to go to 3D, massively parallel systems with chiplets, compute/memory integration to reduce RAM latency, special purpose accelerators using quantum or photonic computation, etc. It does probably mean the free lunch of "faster systems with existing code" is largely over. Of course that free lunch train started to end in the 2000s when clock speeds on conventional chips topped out in the 2-5ghz range. It meant we had to go parallel, a transition very much still in progress. Edit: remember too that there is a TON of performance on the table on today's systems via more efficient slimmed down code. I think we will see the small/simple/efficient trend increase and bloat will be seen as much more embarrassing than it is today. Look at what could be done with efficient code on an 8-bit 64K RAM computer in the 1980s: https://en.wikipedia.org/wiki/GEOS_(8-bit_operating_system) https://en.wikipedia.org/wiki/GEOS_(8-bit_operating_system)
alecco 5y ago
Asianometry has some very good episodes on ASML https://www.youtube.com/results?search_query=asianometry+asml https://www.youtube.com/results?search_query=asianometry+asm... and also relevant their Zeiss episodes https://www.youtube.com/results?search_query=asianometry+zeiss https://www.youtube.com/results?search_query=asianometry+zei...
- bluedays 5y ago
  You couldn't directly link the video?
  - BuildTheRobots 5y ago
    I think the ops point is that for both links there are multiple relevant videos.
    - deleted 5y ago
      [deleted]
MisterTea 5y ago
Fun stuff. I'm actually working on a mechanical part for ASML that goes inside of the vacuum part of the system and deals with the wafers. Very stringent specs and when the final parts are here for processing, ASML engineers will be here to watch.
buran77 5y ago
> the CTO jokingly gave him a plaque emblazoned with the words “Scientifically Accurate But Practically Useless.” ...Until it isn't and it gets your stuff done. The best CTOs I have ever met were far more superficial in how they treated their issues than the best engineers were about theirs (perhaps a sign of being focused more/only on the bigger picture?).
singularity2001 5y ago
Moore's law lives on in Kurzweil's law: The amount of compute you get per dollar doubles every 18 months, as proven by GPUs
- mjburgess 5y ago
  All growth curves which flatten have exponential phases.
  - BizarroLand 5y ago
    80/20 rule comes into effect as well. Without a monumental change in the structure of CPUs, we will only be seeing small steps in performance for the foreseeable future. 5% improvement a generation is good, I am not complaining, but even if there are twice as many transistors in a CPU without the instruction set to take advantage of them and the software written with utilizing the available resources, it's nearly a moot point. I believe we're long past the point where a clock speed boost or a new instruction set can generate any huge leaps in processing power over a single generation, and I would go so far as to say that there is very little practical difference between, say a 6th gen core i7 and an 11th gen i7 from the end users perspective.
easton 5y ago
Direct link: https://www.technologyreview.com/2021/10/27/1037118/moores-law-computer-chips/ https://www.technologyreview.com/2021/10/27/1037118/moores-l...
neonate 5y ago
https://archive.md/TchSb https://archive.md/TchSb
pingec 5y ago
Can anyone explain what role does ASML play in TSMC's advantage over other fabs? Let's say TSMC and other fabs can all source same equipment from ASML, what else exactly does TSMC do better than the others?
redis_mlc 5y ago
ASML machines have billions of lines of code, which is their real moat, and why Japan was permanently displaced in this industry. (Software dev. historically has been considered the lowest-status eng. discipline in Japan, with the lowest salaries to match.)

70 points by mikro2nd 5y ago

Reading the development story and just how long they worked on this, with would-be competitors falling by the wayside the whole time, I'm less surprised than I was that Intel missed the boat on this technology. Intel, and apparently almost everyone else other than TSMC, were skeptical this would work. But now that it does, Intel has some catch-up to do to build fabs using these things to match what TSMC is doing with them.

ballenf 5y ago
The article mentions Intel is slated to get the first next-gen EUV device ("high-NA EUV"). I wonder how much lead time this buys them from when TSMC gets theirs? Presumably would just be a month or two at most, unless Intel is getting more than just the first. If they can produce 55 of the current generation per year, the next generation would be produced at some order of magnitude slower at first.
- ksec 5y ago
  You dont buy a few and expect them to work on latest nodes unless you want capacity constrained launch cycle. So it is likely the whole order for that year would go to Intel if they do intend to use it on their 4nm. TSMC has settled on older generation anyway. Their "slightly" delayed 3nm isn't on GAAFET / Nanowire / Ribbonfet or MBCFET. whatever term they decide to use. ( It is getting worse then their "nm" naming ) and not on High-NA EUV either which is scheduled for their 2nm. Sometime in 2025. So the lead time may be around a year and a bit more. And I keep mentioning this everywhere, on HN or Semiwiki and other places. TSMC is a (very) conservative company. Betting on something exotic and not quite ready isn't their thing.

vadiml 5y ago

They say in that article the Intel will produce chips based on 10nm tech in 2025. However Wikipedia says the Apple M1 chips are currently using 5nm tech... How come?

mnw21cam 5y ago
Different companies call these technologies different things, but they're fairly divorced from the actual minimum feature size these days. Your advertised feature size is a marketing term, so it's going to be gamed to some extent.
detaro 5y ago
There's lots of variation in how companies define their nodes and not really connected to any measurement anymore. I.e. if a company speaks about it's "10nm node" that doesn't mean there is a physical thing 10nm in size (and e.g. Intels 10nm node is often considered to be equivalent to Samsungs 7nm node) - it's better to think of it as a version number in a way. As such, talking about these things gets confusing quickly, and the article also doesn't clarify what exactly it means when it says "10nm in size".

pmlnr 5y ago

"Law" my *ss. At least call it Moore's Belief but rather just forget about it.

martin_balsam 5y ago
The number of people who believe that Moore’s Law is dead doubles every 18 months -Jim Keller
- 1cvmask 5y ago
  That should be Keller’s law
- ksec 5y ago
  Except Jim Keller refers Moore’s Law to transistor improvement and not doubling of anything, whether that is transistor or performance. We broke the 2x graph for some time already. But that doesn't mean we are not getting 1.7x.
Melkman 5y ago
A silicon atom is about 111pm. So 90 atoms is 10nm. What is the minimum size of a feature in atoms before running in to problems with physics?
- rini17 5y ago
  Oh, they ran into problems with physics long ago. And so far solved them.
- marcosdumay 5y ago
  > What is the minimum size of a feature in atoms before running in to problems with physics? About 10nm. High-end chips have been there for ages now. Fighting those problems takes quite a bit of creativity.
- brennanpeterson 5y ago
  As a rule of thumb, about 10 unit cells (5nm). There are some exceptions, but this is a useful number. That means that practically, the smallest conceivable metal pitch is 10nm, the smallest gate is 20. From 5nm, it implies a factor of 10 is left, or about 3-4 nodes.i expect lower scaled nodes at larger delays, but another 15-20 years.

causi 5y ago

saved moore's law When did that happen? Last I checked even Intel's new hotness was struggling to double the IPC of my ancient Haswell.

alecco 5y ago
Moore's Law is doubling transistors per area, not IPC, not Mhz, nor bandwidth.
- gameswithgo 5y ago
  right, which also hasn’t quite been happening lately but the term has changed in popular use to mean something more like “still getting smaller every few years”
- marcosdumay 5y ago
  Moore's Law is doubling the transistors on the most economical package. EUV would have to be cheap to keep Moore's Law alive.
- deleted 5y ago
  [deleted]
api 5y ago
Everyone knew Moore's law was going to be a sigmoid curve, otherwise we'd be getting transistors smaller than atoms which is impossible. Today the term is used as vernacular for "well we are still getting smaller." Nobody knows what the last process node for conventional flat semiconductors will be, but recent speculation is around 1.5nm. Small embedded and low performance chips may have already topped out in a cost/benefit sense. There's no benefit to a 5nm process microcontroller for a coffee maker. The really small nodes may stay reserved for high performance or ultra low power chips. After we really do hit the top of the sigmoid it doesn't mean computers getting more powerful is over. It just means we would have to go to 3D, massively parallel systems with chiplets, compute/memory integration to reduce RAM latency, special purpose accelerators using quantum or photonic computation, etc. It does probably mean the free lunch of "faster systems with existing code" is largely over. Of course that free lunch train started to end in the 2000s when clock speeds on conventional chips topped out in the 2-5ghz range. It meant we had to go parallel, a transition very much still in progress. Edit: remember too that there is a TON of performance on the table on today's systems via more efficient slimmed down code. I think we will see the small/simple/efficient trend increase and bloat will be seen as much more embarrassing than it is today. Look at what could be done with efficient code on an 8-bit 64K RAM computer in the 1980s: https://en.wikipedia.org/wiki/GEOS_(8-bit_operating_system) https://en.wikipedia.org/wiki/GEOS_(8-bit_operating_system)

alecco 5y ago

Asianometry has some very good episodes on ASML https://www.youtube.com/results?search_query=asianometry+asml https://www.youtube.com/results?search_query=asianometry+asm... and also relevant their Zeiss episodes https://www.youtube.com/results?search_query=asianometry+zeiss https://www.youtube.com/results?search_query=asianometry+zei...

bluedays 5y ago
You couldn't directly link the video?
- BuildTheRobots 5y ago
  I think the ops point is that for both links there are multiple relevant videos.
  - deleted 5y ago
    [deleted]

MisterTea 5y ago

Fun stuff. I'm actually working on a mechanical part for ASML that goes inside of the vacuum part of the system and deals with the wafers. Very stringent specs and when the final parts are here for processing, ASML engineers will be here to watch.

buran77 5y ago

> the CTO jokingly gave him a plaque emblazoned with the words “Scientifically Accurate But Practically Useless.” ...Until it isn't and it gets your stuff done. The best CTOs I have ever met were far more superficial in how they treated their issues than the best engineers were about theirs (perhaps a sign of being focused more/only on the bigger picture?).

singularity2001 5y ago

Moore's law lives on in Kurzweil's law: The amount of compute you get per dollar doubles every 18 months, as proven by GPUs

mjburgess 5y ago
All growth curves which flatten have exponential phases.
- BizarroLand 5y ago
  80/20 rule comes into effect as well. Without a monumental change in the structure of CPUs, we will only be seeing small steps in performance for the foreseeable future. 5% improvement a generation is good, I am not complaining, but even if there are twice as many transistors in a CPU without the instruction set to take advantage of them and the software written with utilizing the available resources, it's nearly a moot point. I believe we're long past the point where a clock speed boost or a new instruction set can generate any huge leaps in processing power over a single generation, and I would go so far as to say that there is very little practical difference between, say a 6th gen core i7 and an 11th gen i7 from the end users perspective.

easton 5y ago

Direct link: https://www.technologyreview.com/2021/10/27/1037118/moores-law-computer-chips/ https://www.technologyreview.com/2021/10/27/1037118/moores-l...

neonate 5y ago

https://archive.md/TchSb https://archive.md/TchSb

pingec 5y ago

Can anyone explain what role does ASML play in TSMC's advantage over other fabs? Let's say TSMC and other fabs can all source same equipment from ASML, what else exactly does TSMC do better than the others?

redis_mlc 5y ago

ASML machines have billions of lines of code, which is their real moat, and why Japan was permanently displaced in this industry. (Software dev. historically has been considered the lowest-status eng. discipline in Japan, with the lowest salaries to match.)