21 ms·
Intel 3rd gen Xeon Scalable (Ice Lake): generationally big, competitively small
- totalZero 6y agoKey takeaway for me: "As impressive as the new Xeon 8380 is from a generational and technical stand-point, what really matters at the end of the day is how it fares up to the competition. I’ll be blunt here; nobody really expected the new ICL-SP parts to beat AMD or the new Arm competition – and it didn’t. The competitive gap had been so gigantic, with silly scenarios such as where a competing 1-socket systems would outperform Intel’s 2-socket solutions. Ice Lake SP gets rid of those more embarrassing situations, and narrows the performance gap significantly, however the gap still remains, and is still undeniable."
- marmaduke 6y agoNice to see that AVX512 hasn't died with Xeon Phi. I see it coming out in a number of high end but lightweight notebooks too (Surface Pro with i7 10XXG7, MacBookPro 13" idem). This is a nice way to avoid needing GPU for heavily vectorizable compute tasks, assuming you don't need the CUDA ecosystem.
- 37ef_ced3 6y agoFor example, AVX-512 neural net inference: https://NN-512.com https://NN-512.com Only interesting if you care about price (dollars spent per inference) For raw speed (no matter the price) the GPU wins
- dragontamer 6y agoGPGPU will never really be able to take over CPU-based SIMD. GPUs have far more bandwidth, but CPUs beat them in latency. Being able to AVX512 your L1 cached data for a memcpy will always be superior to passing data to the GPU. With Ice Lake's 1MB L2 cache, pretty much all tasks smaller than 1MB will be superior in AVX512 rather than sending it to a GPU. Sorting 250,000 Float32 elements? Better to SIMD Bitonic sort / SIMD Mergepath (https://web.cs.ucdavis.edu/~amenta/f15/GPUmp.pdf https://web.cs.ucdavis.edu/~amenta/f15/GPUmp.pdf) on your AVX512 rather than spend a 5us PCIe 4.0 traversal to the GPU. It is better to keep the data hot in your L2 / L3 cache, rather than pipe it to a remote computer (even if the 16x PCIe 4.0 pipe is 32GB/s and the HBM2 RAM is high bandwidth once it gets there). -------- But similarly: CPU SIMD can never compete against GPGPUs at what they do. GPUs have access to 8GBs @500GB/s VRAM on the low-end and 40GBs @1000GB/s on the high end (NVidia's A100). EDIT: Some responses have reminded me about the 80GB @ 2000GB/s models NVidia recently released. CPUs barely scratch 200GB/s on the high end, since DDR4 is just slower than GPU-RAM. For any problem where data-bandwidth and parallelism is the bottleneck, that fits inside of GPU-VRAM (such as many-many sequences of large scale matrix multiplications), it will pretty much always be better to compute that sort of thing on a GPU.
- celrod 6y agoFWIW, the A64FX has 1TB/s bandwidth because it has 32GiB of HBM2.
- dragontamer 6y agoAh yes, good point. ------- It should be noted that most CPUs do use DDR4 for good reason: they have an expectation to use more than the capacity of HBM2. GPUs (and a supercomputer CPU, like the A64FX) can rely upon the fact that their workloads are designed for distributed-compute and/or otherwise fit inside of 32GBs or 40GBs. CPUs on the other hand, could very well be reading/writing to a 2TB in-memory database these days, even on a single-socket single-node system like AMD EPYC. That flexibility to have as much (or as little) RAM as the customer demands is a major advantage of traditional CPUs like EPYC or Xeon, which the A64FX cannot partake in. If you need more than 32GBs of RAM, A64Fx is a no-go. That HBM2 is soldered directly onto the package and cannot expand.
- celrod 6y agoYes, and 32 GB seems rather limited for a 48 core chip. While not a "general purpose" CPU, this HPC CPU does show IMO that it's at least possible of making a CPU that does compete in some aspects with what GPUs do. Although an A100 still has twice the bandwidth and over 3x the GFLOPS without tensor cores and more than 6x with.
- ajross 6y agoFWIW: your DRAM numbers are quoting clock speeds and not bandwidth. They aren't linear at all. In fact with enough cores you can easily saturate memory that wide, and CPUs are getting wider just as fast as GPUs are. The giant Epyc AMD pushed out last fall has 8 (!) 64 bit DRAM channels, where IIRC the biggest NVIDIA part is still at 6.
- dragontamer 6y ago> 8 (!) 64 bit DRAM channels Yeah. And at 3200 Mbit/sec, that comes out to 200GB/s. (3200 MHz x 8-bytes (aka 64-bit) == 25GB/s. x8 channels == 200GB/s). > where IIRC the biggest NVIDIA part is still at 6. That's 6x *1024-bit* HBM2 channels. Total bandwidth is 2000GBps, or over 10x the speed of the "8x channel EPYC". Yeah, HBM2 is fat, extremely fat. ---------- *ONE* HBM2 channel offers over 300GBps bandwidth. And the A100 has *SIX* of them. Literally ONE HBM2 channel beats the speed of all 8x DDR4 EPYC memory channels working in parallel.
- api 6y agoThe 2020 Intel MacBook Air and 13" Pro have 10nm Ice Lake with AVX512. The Ice Lake MacBook Air performs pretty well and very close to the Ice Lake Pro, though of course the M1 destroys it.
- bitcharmer 6y agoAVX-512 is an abomination in my field and we avoid it like the plague. It looks like we're not the only ones. Linus has a lot to say about it as well. https://www.phoronix.com/scan.php?page=news_item&px=Linus-Torvalds-On-AVX-512 https://www.phoronix.com/scan.php?page=news_item&px=Linus-To...
- aseipp 6y agoSkylake-X has already had its die shots examined and the AVX-512 register file, the dominant part of the layout, is something like .5 of a single core, so it's not even going to buy you much area for anything if Intel deleted it, the whining about how it's better spent on extra cores by Linus is totally overblown. Ice Lake has also dramatically improved the per-core frequency tuning for client SKUs to the point AVX-512 is quite viable on my laptop with no serious problems; a single thread doing something isn't going to tank anything. Ice Lake-X almost certainly has 2FMAs instead of the 1FMA of client SKUs however, so it'll be interesting to see what the new power licensing situation is, but this is clearly something they've had in the books to improve. The problem is that for the workloads that need specialization, you sometimes really need it. You could also delete the vectorized AES units in your Intel machines too and the general purpose performance wouldn't be affected much, but cryptographic performance specifically would tank, and it turns out, that matters a lot in aggregate for many people. Ultimately there are literally dozens of specialized inactive units on any CPU at any given time that could be "better spent on general purpose units" (which also isn't necessarily true if other architectural choices prevent those units from being utilized effectively). People just like complaining about AVX-512 because it's easily digestible water cooler chat they read about on a blog.
- bitcharmer 6y agoAVX-512 is problematic in multiple ways your comment fails to even touch upon. It impedes latency-sensitive applications due to forced down-clocking taking place for AVX-intensive instruction streams. The other side effect is that it quickly produces extreme heat that not only forces further down-clocking of the core but also taints neighbouring cores with dissipated heat and prevents them from going into turbo. Not everything is about performance in laptops.
- w0mbat 6y ago10nm? I love retro-computing.
- ajross 6y agoAs gets repeated ad nauseum, industry numbering has gone wonky. Intel still hews more or less to the ITRS labelling for its nodes, which means that it's 10nm process has pitches and density values along the same lines as TSMC or Samsung's 7nm processes. This is, indeed, no longer an industry leading density and it lags what you see on "5nm" parts from Apple and Qualcomm. But it's the same density that AMD is using for the Zen 2/3 devices against which this is competing in the datacenter.
- adrian_b 6y agoMaybe the density is the same, but the 10-nm process variant that Intel is forced to use for Ice Lake Server is much worse than the 7-nm TSMC process. It is worse in the sense that at the same number of active cores and the same power consumption, the 10-nm Ice Lake Server can reach only a much lower clock frequency than the 7-nm Epyc, which results in a much lower performance for anything that does not use AVX-512. It is also worse in the sense that the maximum clock frequency when the power limits are not reached is also much worse for the 10-nm process used for Ice Lake Server. Ice Lake Server does not use the improved 10-nm process (SuperFin) that is used for Tiger Lake and it is strongly handicapped because of that.
- ac29 6y agoWhile I'd agree with you that TSMC's current 7nm seems to be better than Intel's current 10nm, comparing Epyc to Ice Lake SP isnt quite the same. Intel is putting (up to) 40 cores on the same die, AMD only puts 8 cores. It looks like AMD has the better method for overall performance, and Intel will likely follow them - in addition to being able to get more cores into a socket, I suspect Intel could also crank frequency higher with less cores per die.
- adrian_b 6y ago
- CSSer 6y agoLately Intel seems to be getting a lot of flack here. As a layperson in the space who's pretty out of the loop (I built a home PC about a decade ago), could someone explain to me why that is? Is Intel really falling behind or dressing up metrics to mislead or something like that? I also partly ask because I feel that I only really superficially understand why Apple ditched/is ditching Intel, although I understand if that is a bit off-topic for the current article.
- tyingq 6y agoLots of shade because they first missed the whole mobile market, then got beat by AMD Zen by missing the chiplet concept and a successful current-gen process size, then finally also overshadowed by Apple's M1. The M1 thing is interesting, because it likely means the next set of ARM Neoverse CPUs for servers, from Amazon and others, will be really impressive. Intel is behind on many fronts.
- mhh__ 6y ago>likely means the next set of ARM Neoverse CPUs from Amazon and others will be really impressive M1 is proof that it can be done, however you can absolutely make a bad CPU for a good ISA so I wouldn't take it for granted.
- tyingq 6y agoMight be a hint as to how much of M1's prowess is just the process size and how much is Apple.
- s_dev 6y ago>Is Intel really falling behind Intel is already behind AMD -- they have no product segment where they are absolutely superior. The means AMD is setting the market pace. On top of this Apple is switching to ARM designed CPUs. This also looks to be a vote of no confidence in Intel. The consensus seems to be that Intel who have their own fabs -- never really nailed anything under 14nm and are now being outcompeted.
- jvanderbot 6y agoFrom Anandtech[1]: "As impressive as the new Xeon 8380 is from a generational and technical stand-point, what really matters at the end of the day is how it fares up to the competition. I’ll be blunt here; nobody really expected the new ICL-SP parts to beat AMD or the new Arm competition – and it didn’t. The competitive gap had been so gigantic, with silly scenarios such as where a competing 1-socket systems would outperform Intel’s 2-socket solutions. Ice Lake SP gets rid of those more embarrassing situations, and narrows the performance gap significantly, however the gap still remains, and is still undeniable." This sounds about right for a company fraught with so many process problems lately: Play catch up for a while and hope you experience fewer in the future to continue to narrow the gap. "Narrow the gap significantly" sounds like good technical progress for Intel. But the business message isn't wonderful. 1. https://www.anandtech.com/show/16594/intel-3rd-gen-xeon-scalable-review/11 https://www.anandtech.com/show/16594/intel-3rd-gen-xeon-scal...
- jvanderbot 6y agoFurthermore: "At the end of the day, Ice Lake SP is a success. Performance is up, and performance per watt is up. I'm sure if we were able to test Intel's acceleration enhancements more thoroughly, we would be able to corroborate some of the results and hype that Intel wants to generate around its product. But even as a success, it’s not a traditional competitive success. The generational improvements are there and they are large, and as long as Intel is the market share leader, this should translate into upgraded systems and deployments throughout the enterprise industry. Intel is still in a tough competitive situation overall with the high quality the rest of the market is enabling."
- jandrese 6y agoI found it a little weird that they conclusions section didn't mention the AMD or ARM competition at all, given that the Intel chip seemed to be behind them in most of the tests.
- jvanderbot 6y agoYou mean OP didn't? Yes, that's probably standard PR to focus on strengths rather than competition.
- paulpan 6y agoTLDR from Anandtech is that while this is a good improvement over previous gen, it still falls behind AMD (Epyc) and ARM (Altra) counterparts. What's somewhat alarming is that on a per-core comparison (28-core 205W designs), the performance increase can be a wash. Doesn't bode well for Intel as both their competitors are due for refreshes that will re-widen the gap. Key question will be how quickly Intel will shift to the next architecture, Sapphire Rapids. Will this release be like the consumer/desktop Rocket Lake? E.g. just a placeholder to essentially volume test the 10nm fabrication for datacenter. Probably at least a year out at this point since Ice Lake SP was supposed to be originally released in 2H2020.
- gsnedders 6y ago> Key question will be how quickly Intel will shift to the next architecture, Sapphire Rapids. Will this release be like the consumer/desktop Rocket Lake? E.g. just a placeholder to essentially volume test the 10nm fabrication for datacenter. Probably at least a year out at this point since Ice Lake SP was supposed to be originally released in 2H2020. Alder Lake is meant to be a consumer part contemporary with Sapphire Rapids, which is server only. They're likely based on the same (performance) core, with Adler Lake additionally having low-power cores. Last I heard the expectation was still that these new parts would enter the market at the end of this year.
- ChuckMcM 6y agoI found the news of Intel releasing this chip quite encouraging. If they have enough capacity on their 10nm node to put it into production then they have tamed many of the problems that were holding them back. My hope is that Gelsinger's renewed attention to engineering excellence will allow the folks who know how to iron out a process to work more freely than they did under the previous leadership. That said, fixing Intel is a three step process right? First they have to get their process issues under control (seems like they are making progress there). Second, they need to figure out the third party use of that process so that they can bank some some of revenue that is out there from the chip shortage. And finally, they need to answer the "jelly bean" market, and by that we know that "jelly bean" type processors have become powerful enough to be the only processor in a system so Intel needs to play there or it will lose that whole segment to Nvidia/ARM.
- judge2020 6y agoProduction for a datacenter CPU is not the same as production for datacenter + enthusiast-grade consumer CPUs like Zen 3 currently achieves, unfortunately. Rocket lake being backported to 14nm is still not a good sign for actual production volume, although it probably means next generation will be 10nm all the way.
- willis936 6y agoDatacenter CPUs are much larger than consumer parts and yield goes down with the square of the die area. They start with these because the margins go up faster than square of the die area.
- ASpaceCowboi 6y agowill this work on the latest mac pro? Probably not right?
- Pr0GrasTiNati0n 6y agoAnd only 20 of those cores have back doors.....lulz
- Sephr 6y agoAs disappointing as the perf is for server workloads, what I'm really interested in is SLI gaming performance. I can imagine that this would be a boon for high end gaming with multiple x16 PCIe 4.0 slots and 8 DDR4 channels. SLI really shines on HEDT platforms, and this is probably the last non-multi-chip quasi-HEDT CPU for a while with this kind of IO. (Yes, I know SLI is 'dead' with the latest generation of GPUs)
- zamadatix 6y agoThese would be absolute trash for SLI performance vs top end standard consumer desktop parts. The best SKU has a peak boost clock of 3.7 GHz, the core to core latencies are about twice as high as the desktop parts, and the memory+PCIe bandwidth mean little to nothing for gaming performance (remember SLI bandwidth goes over a dedicate bridge as well) which is highly sensitive to latencies instead.
- intricatedetail 6y agoWhy Intel even bothers releasing products that don't bring anything new and worthwhile to the table? This is such a massive waste of time, resources and environment.
- lifeisstillgood 6y agoThis might be a very dumb question but it always bothered me - silicon wafers are always shown as great circles, but processor dies are obviously square. But it looks like the etching etc goes right to the circular edges - wouldn't it be better to leave the dead space untouched?
- pas 6y agoI think these are just press/PR wafers and real production ones don't pattern on the edge. (First of all it takes time, and in case of EUV it means things amortize even faster, because every shot damages the "optical elements" a bit.) edit: it also depends on how many dies the mask (reticle) has on it. Intel uses one die reticles, so i. theory their real wafers have no situation in which they have partial dies at the edge.
- dogma1138 6y agoReal wafers have the chip patterning going to the edge and this can results and often does in partial dies. There is no reason not too so this and the edges are also often used for calibration and (potentially) destructive testing. The only area of the wafer that will not be exposed is the notch, it’s always on one side of the circle and it’s used for moving the wafer around, this is why you often see wafers with one of the sides cut off giving it the flat tire shape.
- w0utert 6y agoMost semiconductor production processes like etching, doping, polish etc are done on the full wafer, not on individual images/fields. So there is nothing to be gained there in terms of production efficiency. The litho step could in theory be optimized by skipping incomplete fields at the edges, but the reduction in exposure time would be relatively small, especially for smaller designs that fit multiple chips within a single image field. I imagine it would als introduce yield risk because of things like uneven wafer stress & temperature, higher variability in stage move time when stepping edge fields vs center fields, etc.
- andromeduck 6y ago
- bitL 6y agoCan we soon expect a 10980XE successor to have some Threadripper competitor as well? Or is it just Xeons?
- adreamingsoul 6y agoWhich orgs today still have technical leadership?