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Die Shots of the Raspberry Pi RP2040
- mmastrac 6y agoAlternative Twitter thread: https://twitter.com/johndmcmaster/status/1355092011829719046 https://twitter.com/johndmcmaster/status/1355092011829719046
- jacquesm 6y agoYes, much better, thank you. (I made the same suggestion)
- dang 6y agoOk, we'll change to that from https://blog.adafruit.com/2021/01/29/die-shots-of-the-raspberry-pi-rp2040-chip-teardown-dieshot-reverseengineering-piday-johndmcmaster-raspberry_pi/ https://blog.adafruit.com/2021/01/29/die-shots-of-the-raspbe.... Thanks!
- mobilio 6y agoAttention to detail is amazing!
- breck 6y agoA simple stack of these images with a CSS offset (to give it a 3-d look) would be great. Edit: his zoomable image is even better (https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x=2432&y=2360&z=1 https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x...)
- breck 6y agoOh wow this thread (and his whole Twitter account) is gold. thanks for sharing. Edit: this zoomable image is great (https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x=2432&y=2360&z=1 https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x...)
- 725686 6y agoThe resistor value captcha at the end of the page is golden.
- war1025 6y agoHow do I interact with it? I tried picking the colors, but nothing I tried did anything.
- allenu 6y agoYou can drag the slider. Clicking doesn't seem to work.
- war1025 6y agoDoesn't work for me on Firefox. I'm guessing it works on Chrome, but it also would sort of surprise me that a maker website wouldn't test against Firefox. Maybe I'm giving them too much credit.
- mbreese 6y agoFrom the twitter thread, someone said it was fabbed by TSMC at 40nm. I wonder, with the cutting edge moving to smaller and smaller processes (5nm, etc)... how much of the older/larger capacity can be reused? Meaning, are we about to see a ton of cheaper chips like this RP2040 that are using older/slower/obsolete fab capacity? Or is the same equipment able to be used across a family of process sizes? In other words, once TSMC has X amount of capacity on 40nm, is that capacity always around and fixed to 40nm? If so, I imagine that creating new chips that don't need to be super fast will just become super cheap.
- TorKlingberg 6y agoOlder processes available for cheap are not a new thing. They do indeed stay around until TSMC decide they're no longer worth running. It's not always cheaper as a larger process wastes more wafer.
- geerlingguy 6y agoI believe Eben Upton mentioned in a Twitter thread somewhere that they were getting thousands of chips off each wafer at the current node size? Only had to order like 20 or 40 wafers for the first production run, something like that.
- avian 6y agoMicroelectronics cutting edge has been moving to smaller processes for the past 70 years. This is nothing new. If anything, the progress has slowed down. Some fabs get closed down/rebuilt for a different process, some stay and produce parts that don't benefit from higher densities. Last I checked some ICs still get produced in 0.35 um processes. You don't need billions of transistors for an opamp.
- swalsh 6y agoFor how long is the equipment for these fabs amortized?
- baybal2 6y ago
- AbraKdabra 6y agoHow does one of those die get made at all? It's such a minuscule small scale and it has such detail I cannot even comprehend how those components get "stamped" there, it's black magic.
- swalsh 6y agoIt's not really "Stamped". It's more of a photographic process. My basic understanding is that they apply a photographic reactive chemical, expose it. From there they apply another chemical process to form an oxidation layer, and then use an acid process to "etch" away material creating channels of positively charged particles. Then they can apply a mask, and throw tiny amounts of metal which will become the gate.
- geerlingguy 6y agoThe process of photolithography [1] involves a lot of complex optics, and interestingly you find a lot of lens manufacturers involved in it since it involves a lot of steps where light (e.g. lasers in this case) gets passed through a set of very precise optics until it hits the wafer and etches in the correct pattern from a larger 'reference copy'. [1] https://en.wikipedia.org/wiki/Photolithography https://en.wikipedia.org/wiki/Photolithography
- baybal2 6y agoActually, the process of actually "stamping" ICs mechanically is being pursued to make IC production even more cheaper. https://en.m.wikipedia.org/wiki/Nanoimprint_lithography https://en.m.wikipedia.org/wiki/Nanoimprint_lithography
- auxym 6y agoI like this animation showing how a FET is fabricated using photolithography processes: https://micro.magnet.fsu.edu/electromag/java/transistor/index.html https://micro.magnet.fsu.edu/electromag/java/transistor/inde...
- blcArmadillo 6y ago
- jsmith45 6y agoI'm suprised that even the CPU cores are implemented just as a sea of standard cells. It is common to have them be macros containing a clearly separate datapath and control logic. On the other hand, the fact that the prototyping was done on an FPGA makes this less surprising. Sea of cells is certainly easier to update, and less work than any form of manual datapath when migrating from FPGA to ASIC.
- mlyle 6y agoYup. This is pretty clearly a case of getting it to run on an FPGA and using a commercial FPGA to ASIC service instead of spending a lot of time in synthesis and validation. Mask costs can be cheaper this way, too, because some layers can be invariant between different parts.
- deleted 6y ago[deleted]
- ohazi 6y ago> using a commercial FPGA to ASIC service This was not an FPGA conversion. "Commercial FPGA to ASIC service" usually refers to Altera/Intel's HardCopy or Xilinx's EasyPath. EasyPath is where Xilinx sells you defective FPGAs for way cheaper, but with just enough of the right parts of the fabric working that your design can still fit and work properly. HardCopy is where Altera sells you a small number of metal mask layers to implement your design on a much smaller/faster sea-of-gates style ASIC that mimics the non-reprogrammable parts of the target FPGA. The Raspberry Pi Foundation did neither of these things. They tested their design on an FPGA, which is common, and then used standard cell libraries and IP blocks provided by the fab and their partners to get through the normal ASIC workflow. It turns out it's just easier and faster to tell the tools to automatically place and route the core complex than to do a careful floorplan. Also given that the RP2040 is apparently "very overclockable" (the PIO bitbanged HDMI output bumped the clock to something like double the nominally guaranteed maximum), the merits of doing it this way seem sound.
- happycube 6y ago
- dboreham 6y agoInteresting. I did not realize wire bonding is still used on large devices.
- tomcam 6y agoNot a big fan of Twitter but I have to say it was an amazing use of the medium.
- myself248 6y agoHow common is it to use copper bondwires? I thought these were always gold.
- MuffinFlavored 6y agocheap microcontrollers: ESP32: WiFI, no USB RP2040: USB, no WiFi :(
- jesse_cureton 6y agoThe "Arduino Nano RP2040 Connect" is an RP4040 board slated to be coming soon that will provide WiFi and Bluetooth. I expect we'll see more RP2040 devboards & SOMs coming soon that fill the connectivity niche.
- MuffinFlavored 6y agoBluetooth? I’m looking for WiFi + USB.
- mmoskal 6y agoESP32-S2 has both WiFi and USB. It's essentially (the classic) ESP32 cut to a single core, 320KB RAM, and with Bluetooth removed; however it does include USB. There's also ESP32-S3 which is dual core, with more RAM, USB, and Bluetooth, but I'm not sure any boards are available yet. All of that not to be confused with ESP32-C3 which is a single-core RISC-V without USB. And yes, their naming is confusing. edit: Adafruit has some boards with ESP32-S2. If you get a random board from elsewhere, there are good chances it will come with a USB-to-serial chip, which you don't want if you need to use native USB. So check.
- MuffinFlavored 6y ago> ESP32-S2 has both WiFi and USB USB 1.0/1.1 right? Not 2.0?
- samstave 6y agoOne of my regrets from when I worked at Intel was that we had die plans on 36x48 printouts in the lab - and they were beautiful, I wish I had taken them home - I would love to have some framed on my walls now.
- jacquesm 6y agoWhy not link to the original thread instead? https://twitter.com/johndmcmaster/status/1355092011829719046 https://twitter.com/johndmcmaster/status/1355092011829719046
- dang 6y agoChanged from https://blog.adafruit.com/2021/01/29/die-shots-of-the-raspberry-pi-rp2040-chip-teardown-dieshot-reverseengineering-piday-johndmcmaster-raspberry_pi/ https://blog.adafruit.com/2021/01/29/die-shots-of-the-raspbe.... Thanks!
- mrlonglong 6y agoMy pair arrived last Friday. With bare metal coding I have its LED blinking. Now I'm just thinking how to bring up a very small SMP capable UNIX clone in it. If the PDP/11 could do it I see no reason why it can't be done on the Pico. Fuzix exists for 6502 and Z80 processors and these are tiny!