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Is there a quantification of "high performance"? It will obviously be much lower than the IPC of an actual high performance CPU (modern x86-64), but how big is

Is there a quantification of "high performance"? It will obviously be much lower than the IPC of an actual high performance CPU (modern x86-64), but how big is the difference? And how does it compare to typical mobile processors?

NieDzejkob 6y ago
I believe the closest measurement would be in Table VII on page 8 of the paper: http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT'19.pdf http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashim...
- childintime 6y ago
  "In comparison to the BOOM, the RSD achieved 2.5-times higher DMIPS and 1.9-times higher DMIPS/MHz", which should be comparable to ARM cores around 4 years ago.
  - Veedrac 6y ago
    Note that BOOM is now on v3[1], which claims to be 3.93 DMIPS/MHz, or about twice RSD. [1] https://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CARRV2020.pdf https://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CAR...
    - deleted 6y ago
      [deleted]
- jhallenworld 6y ago
  RV32IM, 2.04 DMIPS/MHz, 95.3 MHz, 15K LUTs, 8K LUT FFs, 6 BRAMs on Zynq 7020. I'm curious if this will work on Lattice ECP5- I'm not really sure if Synplify supports system verilog to the same degree as the Xilinx tools. ECP5 is interesting because it's a $10 FPGA..
  - mhh__ 6y ago
    At a glance I think it would fit although I might be thinking of the bigger ECP5s which are in the same price bracket as some Zynqs
  - mithro 6y ago
    FWIW Google is working on improving the support for SystemVerilog in open source tools. On the developer tooling side, there is https://github.com/google/verible https://github.com/google/verible for linting, code formatting and code indexing. On the actual compilation side with there are https://github.com/alainmarcel/Surelog https://github.com/alainmarcel/Surelog and https://github.com/alainmarcel/UHDM https://github.com/alainmarcel/UHDM which are then being coupled with open source tools like Yosys to allow targeting Xilinx 7 Series and Lattice ECP5 FPGA ICs with fully open source flows using fully open source FPGA tools like symbiflow.github.io
zurn 6y ago
It's targeting small FPGAs, comparisons to full custom designs wouldn't be very fair.
- adwn 6y ago
  "high-performance" is relative, so they need to compare it to something at all.
  - chungus_khan 6y ago
    I would imagine it is high-performance within its own domain: soft microprocessors. There isn't much danger of something like this being used outside of domains where it is relevant, so just calling it "high-performance" gets the message across fairly well to anyone who would actually need it. I can't comment on how well it performs myself without testing it, but a quick skim of the paper reveals that it apparently performs well in comparison to its rival open-source out-of-order soft processor. Comparing soft processors to other soft processors is fairly easy if they can both run on the same hardware, but comparing them to real silicon is inherently kind of meaningless, as they don't really compete at the moment, and the performance of the design in absolute terms will depend on the FPGA it is implemented on. Nonetheless, you could compare the raw numbers presented in the paper for curiosity's sake and see that indeed, it isn't very fast compared to modern silicon processors.
    - adwn 6y ago
      Sorry, what I meant was: They need to present benchmark results (preferably against other soft-core processors, of course) to claim the "high-performance" attribute. A single row of a synthetic benchmark against only two other contenders is a little ... lacking.
mhh__ 6y ago
This has 5 backend pipelines, which I would say is getting there speed-wise. I think AMD Zen has 10 execution pipelines to play with, although the exact structure is usually not commented upon so I don't know how long they are. It's 32 bit so it's not desktop-class necessarily but this should blow a microcontroller out of the sky, for scale.
- swiley 6y ago
  Do you really want pipelinning on a microcontroller though?
  - mhh__ 6y ago
    Why not? I think Cortex-M3 has a 3 stage pipeline, obviously I would not expect the 0.01$ chinese ones to have one. It's worth saying here, that a big ooo CPU is pipelines differently to a small/old risc processor - even amongst discussions about compiler optimizations people still use terminology like pipeline stall, when a modern CPU has a pipeline that handles fetching an instruction window, finding dependencies, doing register renaming and execution, that pipeline is not like an old IF->IF->EX->MEM->WB - it won't stall in the same way a pentium 5 did. The execution pipes themselves have a more familiar structure.
    - gmueckl 6y ago
      Not sure about Cortex-M3, but I can confirm that the Cortex-M4 has a pretty basic 3 stage in order pipeline that gets flushed on branches. So unless there are caches between the core and memory (I think some STM32 have that), that CPU is still trivially deterministic.
      - makapuf 6y ago
        Yes, m4 from stm have art accelerator (cache memory) which make them less deterministic (but much faster) for flash access. See https://www.st.com/en/microcontrollers-microprocessors/stm32f4-series.html https://www.st.com/en/microcontrollers-microprocessors/stm32...
Symmetry 6y ago
It seems broadly comparable to an ARM Cortex A9 in width and reorder depth but it seems to be using a lot more pipeline stages to do that. Probably that's because they had less engineer-years to invest in the design than ARM did. It looks like it's using pure automatic synthesis so the clock speed will tend to be lower on equivalent process nodes too. The big question is how accurate the prefetcher and branch predictors are. It's entirely possible for an 2 issue out of order core to be slower than 2 issue in order core if the later is significantly better at speculating. Still, that's a good bit of work they should be proud for putting out there and I hope other people build on it. EDIT: Oh, wait, they don't mention register renaming. Hmm, well, I guess no speculating over multiple iterations of a loop then. EDIT2: No, the PDF the link mentions a rename unit. http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT'19.pdf http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashim...

NieDzejkob 6y ago

I believe the closest measurement would be in Table VII on page 8 of the paper: http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT'19.pdf http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashim...

childintime 6y ago
"In comparison to the BOOM, the RSD achieved 2.5-times higher DMIPS and 1.9-times higher DMIPS/MHz", which should be comparable to ARM cores around 4 years ago.
- Veedrac 6y ago
  Note that BOOM is now on v3[1], which claims to be 3.93 DMIPS/MHz, or about twice RSD. [1] https://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CARRV2020.pdf https://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CAR...
  - deleted 6y ago
    [deleted]
jhallenworld 6y ago
RV32IM, 2.04 DMIPS/MHz, 95.3 MHz, 15K LUTs, 8K LUT FFs, 6 BRAMs on Zynq 7020. I'm curious if this will work on Lattice ECP5- I'm not really sure if Synplify supports system verilog to the same degree as the Xilinx tools. ECP5 is interesting because it's a $10 FPGA..
- mhh__ 6y ago
  At a glance I think it would fit although I might be thinking of the bigger ECP5s which are in the same price bracket as some Zynqs
- mithro 6y ago
  FWIW Google is working on improving the support for SystemVerilog in open source tools. On the developer tooling side, there is https://github.com/google/verible https://github.com/google/verible for linting, code formatting and code indexing. On the actual compilation side with there are https://github.com/alainmarcel/Surelog https://github.com/alainmarcel/Surelog and https://github.com/alainmarcel/UHDM https://github.com/alainmarcel/UHDM which are then being coupled with open source tools like Yosys to allow targeting Xilinx 7 Series and Lattice ECP5 FPGA ICs with fully open source flows using fully open source FPGA tools like symbiflow.github.io

zurn 6y ago

It's targeting small FPGAs, comparisons to full custom designs wouldn't be very fair.

adwn 6y ago
"high-performance" is relative, so they need to compare it to something at all.
- chungus_khan 6y ago
  I would imagine it is high-performance within its own domain: soft microprocessors. There isn't much danger of something like this being used outside of domains where it is relevant, so just calling it "high-performance" gets the message across fairly well to anyone who would actually need it. I can't comment on how well it performs myself without testing it, but a quick skim of the paper reveals that it apparently performs well in comparison to its rival open-source out-of-order soft processor. Comparing soft processors to other soft processors is fairly easy if they can both run on the same hardware, but comparing them to real silicon is inherently kind of meaningless, as they don't really compete at the moment, and the performance of the design in absolute terms will depend on the FPGA it is implemented on. Nonetheless, you could compare the raw numbers presented in the paper for curiosity's sake and see that indeed, it isn't very fast compared to modern silicon processors.
  - adwn 6y ago
    Sorry, what I meant was: They need to present benchmark results (preferably against other soft-core processors, of course) to claim the "high-performance" attribute. A single row of a synthetic benchmark against only two other contenders is a little ... lacking.

mhh__ 6y ago

This has 5 backend pipelines, which I would say is getting there speed-wise. I think AMD Zen has 10 execution pipelines to play with, although the exact structure is usually not commented upon so I don't know how long they are. It's 32 bit so it's not desktop-class necessarily but this should blow a microcontroller out of the sky, for scale.

swiley 6y ago
Do you really want pipelinning on a microcontroller though?
- mhh__ 6y ago
  Why not? I think Cortex-M3 has a 3 stage pipeline, obviously I would not expect the 0.01$ chinese ones to have one. It's worth saying here, that a big ooo CPU is pipelines differently to a small/old risc processor - even amongst discussions about compiler optimizations people still use terminology like pipeline stall, when a modern CPU has a pipeline that handles fetching an instruction window, finding dependencies, doing register renaming and execution, that pipeline is not like an old IF->IF->EX->MEM->WB - it won't stall in the same way a pentium 5 did. The execution pipes themselves have a more familiar structure.
  - gmueckl 6y ago
    Not sure about Cortex-M3, but I can confirm that the Cortex-M4 has a pretty basic 3 stage in order pipeline that gets flushed on branches. So unless there are caches between the core and memory (I think some STM32 have that), that CPU is still trivially deterministic.
    - makapuf 6y ago
      Yes, m4 from stm have art accelerator (cache memory) which make them less deterministic (but much faster) for flash access. See https://www.st.com/en/microcontrollers-microprocessors/stm32f4-series.html https://www.st.com/en/microcontrollers-microprocessors/stm32...

Symmetry 6y ago

It seems broadly comparable to an ARM Cortex A9 in width and reorder depth but it seems to be using a lot more pipeline stages to do that. Probably that's because they had less engineer-years to invest in the design than ARM did. It looks like it's using pure automatic synthesis so the clock speed will tend to be lower on equivalent process nodes too. The big question is how accurate the prefetcher and branch predictors are. It's entirely possible for an 2 issue out of order core to be slower than 2 issue in order core if the later is significantly better at speculating. Still, that's a good bit of work they should be proud for putting out there and I hope other people build on it. EDIT: Oh, wait, they don't mention register renaming. Hmm, well, I guess no speculating over multiple iterations of a loop then. EDIT2: No, the PDF the link mentions a rename unit. http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT'19.pdf http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashim...