5 ms·
The whole digital ASIC synthesis flow revolves around timing closure i.e. satisfying setup and hold at max possible clock speed. I guess we may even have to in
by rathel 6y ago
The whole digital ASIC synthesis flow revolves around timing closure i.e. satisfying setup and hold at max possible clock speed.
I guess we may even have to invent a new HDL to pursue asynchronous paradigm efficiently.
- gradschool 6y agoTrue, but inventing a new language for asynchronous hardware wouldn't be as big of a job as reinventing an industry standard like VHDL. Something like a small lightweight concurrent process description formalism with a Petri net based operational semantics would do nicely, and such things have been well understood for decades. The hard part is for it to gain traction.
- rathel 6y agoAs Moore's law slows down, this time for real, there have been a few unorthodox ideas lately. 3DIC, or Cerebras' whole-wafer CPU. This looks like a thing worthy pursuing. With free money and big corps racing for a market first (disruptors trying not to be disrupted), who knows. I wonder how much in terms of power-performance-area can be gained from going asynchronous.
- gradschool 6y agoThere have been many quantitative studies presented over the years at the IEEE Async conferences [1]. The best use cases until now have been niche applications calling for ultra-low power where performance isn't too critical. [1] https://asyncsymposium.org/ https://asyncsymposium.org/
- Junk_Collector 6y agoLadder logic already exists and was designed for documenting and programming asynchronous clock-less computers. The problem is that it's like programming C++ in the early 90's where every hardware vendor sells you their own proprietary implementation.
- orbifold 6y agoThis has been tried before: https://academic.oup.com/comjnl/article-abstract/45/1/12/338521?redirectedFrom=fulltext https://academic.oup.com/comjnl/article-abstract/45/1/12/338...
- marcosdumay 6y agoEven performance specification gets harder. How does one benchmark the latest AMD and Intel processors if performance is different for each unit (and completely changes for each workload)? Asynchronous circuits are full of promises (the largest ones on the low power segment), the reason they are not standard is because the are hard.
- gradschool 6y agoAren't we heading for the same problem the way things are going with dynamic frequency scaling in AMD and Intel processors? How do you predict when a particular workload running a little hotter than anticipated will make it kick in? If the answer is to benchmark them at the factory under carefully controlled conditions and reject those that don't fall within a narrow range, then what's the difference?
- marcosdumay 6y agoIt's similar. The difference is that there are way more dimensions in asynchronous processors. Anyway, when I was studying the subject, the one problem people wrote about was testing. I think the GP's problem and the one I pointed can only get some attention after tests get reasonably solved, and they both may be easier than they look like.
- dnautics 6y ago> the reason they are not standard is because the are hard. With your first sentence, I was really hoping that the punchline was going to be "because they are hard to market"... Not only because superficially I'm a cynic, but also because it implies that there's some hope since the MHz/GHz wars are probably at their end or near their end.
- marcosdumay 6y agoThey are hard at every dimension. To market included. But it doesn't get much attention right now because people are still stuck at the designing, building and testing stages.
- ekiwi 6y agoYou also have to keep in mind that modern flows can already automatically place more area/power efficient but slower transistors on the non-critical paths. Thus signals can get balanced and the wasted area/performance is not as big as one might think.