4 ms·

Well a simple CPU is much more efficient then a complex one. A modern AMD/intel uses very few gates to implement the arithmetic. we are talking ~1% of the gate

Well a simple CPU is much more efficient then a complex one. A modern AMD/intel uses very few gates to implement the arithmetic. we are talking ~1% of the gates actually do the work. The rest is taken up by Cashes, Schedulers, Branch predictors, Decoders, and a load of other stuff that is designed to speed up the CPU to get good single core performance. all this extra hardware takes up a lot of power. Here is an interesting thought experiment: On a large die you could (theoretically) today fit say one million Motorola 68000 Processors. If you clocked that at 5Ghz it would in theory be about 1000 times faster then a Ryzen 7 using the same power. But it would still mean that each core would be hundreds of times slower then a Ryzen core. It would be almost impossible to write programs that would utilize all one million cores effectively enough to make a program run faster on this hardware than it does on a Ryzen CPU. Right now RISC-V is very simple this means it draws very little power. The problem is that it doesn't scale. The RISC-V instruction set is not one that makes it easy to add all the optimizations that one wants to add for a high performance CPU. Its a bit like saying that an ant is more efficient than a bulldozer, yes, that's technically true, but trying to coordinating a million ants to build a road is a lot less efficient then just using a bulldozer.

api 6y ago
Aren't GPUs a bit like your example but not quite as extreme? The CPU you describe would be great for embarrassingly parallel simulation, machine learning, and similar tasks. I wish there was such a thing. Another thought that I’ve had for a while is that Intel’s Itanium was maybe a good idea badly executed or before it’s time. If you really could offload a lot of that to the compiler you could in theory maintain a lot of single thread performance while having far more cores.
- quelsolaar 6y ago
  Yes, you are correct! GPUs are essentially, very many simpler cores on a big die, and the reason it works is that the programing model is inherently parallel. (You almost always want to compute many pixels) GPU "cores" are different because they have graphics specific instructions like texture lookups. They are also different because you want to run the exact same program on many cores at once. So you have have one instruction decoder/dispatcher that control more then one core. This leads to some weird behavior, like if you have a branch in shader code, all cores may compute both branches, but then each core may mask away the result of what ever branch the specific core shouldn't have taken.
  - imtringued 6y ago
    That's a really weird explanation of SIMD. There are big fat cores in GPUs but each core can process the same instruction stream 32 or 64 times but with different data. If there is only one core but two branches have to be taken it is obvious that the core has to process one branch after the other. Your "there are cores inside my cores" explanation is what's causing the confusion.
  - MaxBarraclough 6y ago
    > if you have a branch in shader code, all cores may compute both branches As imtringued suggests, that's not quite right. In SIMD terms, all lanes of the core will be 'along for the ride' in case of control-flow diverging. The core must run the instructions for both branches, effectively disabling and re-enabling its various lanes as necessary. When disabled, a lane does no work. What SIMD calls a lane, SIMT calls a work-item or (perhaps more confusingly) a thread. The term 'core' refers to the level at which there is independent control-flow, much like in CPUs. See https://en.wikipedia.org/wiki/Single_instruction,_multiple_threads https://en.wikipedia.org/wiki/Single_instruction,_multiple_t...
- seniorivn 6y ago
  there is a microprocessor design that attemps to do just that https://en.wikipedia.org/wiki/MCST https://en.wikipedia.org/wiki/MCST it's a russian company, heavily backed by russian government/army/3letteragencies it's hard to tell how successful they are, but there are some benchmarks https://github.com/EntityFX/anybench/blob/master/results/e2k_compare.md https://github.com/EntityFX/anybench/blob/master/results/e2k...
MayeulC 6y ago
> On a large die you could (theoretically) today fit say one million Motorola 68000 Processors. If you clocked that at 5Ghz it would in theory be about 1000 times faster then a Ryzen 7 using the same power. Right. Then, you have to consider how to supply power to all these transistors switching at once, which would well be in the ~10-100A range and beyond. So you have to figure out how not to have it melt (dark silicon, chiplets to have a lower power/area ratio, etc). And once you have it not melt, you have to figure out a way of making it useful: keeping the processors fed with data. Because even the algorithms that crunch just a few variables need to be supplied with those, as well as instructions, etc. This ends up sucking a lot of energy, when you have to clock long lines at 5GHz times the number of CPUs times bus width (you can trade hertz for bus width). To avoid this, we use caches. Good luck keeping your CPU count at 1M with the area SRAM needs. AMD GPUs have been memory bandwidth-starved for a few years now, their latest generation features a whooping 128MB cache. Adiabatic/reversible computing is another way to get around that, but we're not there yet, and isn't a silver bullet either. Von neumann architectures is the thing that doesn't scale. In my opinion, we are going to go back to specialized computing, especially since Moore's Law left us in the cold a few years ago. And RISC-V is quite extensible, which makes it relatively suitable for specialized architectures.
- quelsolaar 6y ago
  You are right, I'm simplifying a lot. I'm ignoring all kinds of issues like how all one million cores would communicate with memory or each other. I hope it at least illustrates that Perfomance / per watt is nice, but unless the perfomance is good enough to be ballpark where you need it, it doesnt matter too much. If there was a dual core CPU where each core ran twice as fast as the fastest Intel/AMD core at the same Watt as an 8 Core Intel/AMD CPU, It would sell like hot cakes, even if it was half the Performance per Watt.
toasted_flakes 6y ago
> yes, that's technically true Not even in this case, the performance and energy numbers they got for CoreMark on the M1 are off by an order of magnitude

api 6y ago

Aren't GPUs a bit like your example but not quite as extreme? The CPU you describe would be great for embarrassingly parallel simulation, machine learning, and similar tasks. I wish there was such a thing. Another thought that I’ve had for a while is that Intel’s Itanium was maybe a good idea badly executed or before it’s time. If you really could offload a lot of that to the compiler you could in theory maintain a lot of single thread performance while having far more cores.

quelsolaar 6y ago
Yes, you are correct! GPUs are essentially, very many simpler cores on a big die, and the reason it works is that the programing model is inherently parallel. (You almost always want to compute many pixels) GPU "cores" are different because they have graphics specific instructions like texture lookups. They are also different because you want to run the exact same program on many cores at once. So you have have one instruction decoder/dispatcher that control more then one core. This leads to some weird behavior, like if you have a branch in shader code, all cores may compute both branches, but then each core may mask away the result of what ever branch the specific core shouldn't have taken.
- imtringued 6y ago
  That's a really weird explanation of SIMD. There are big fat cores in GPUs but each core can process the same instruction stream 32 or 64 times but with different data. If there is only one core but two branches have to be taken it is obvious that the core has to process one branch after the other. Your "there are cores inside my cores" explanation is what's causing the confusion.
- MaxBarraclough 6y ago
  > if you have a branch in shader code, all cores may compute both branches As imtringued suggests, that's not quite right. In SIMD terms, all lanes of the core will be 'along for the ride' in case of control-flow diverging. The core must run the instructions for both branches, effectively disabling and re-enabling its various lanes as necessary. When disabled, a lane does no work. What SIMD calls a lane, SIMT calls a work-item or (perhaps more confusingly) a thread. The term 'core' refers to the level at which there is independent control-flow, much like in CPUs. See https://en.wikipedia.org/wiki/Single_instruction,_multiple_threads https://en.wikipedia.org/wiki/Single_instruction,_multiple_t...
seniorivn 6y ago
there is a microprocessor design that attemps to do just that https://en.wikipedia.org/wiki/MCST https://en.wikipedia.org/wiki/MCST it's a russian company, heavily backed by russian government/army/3letteragencies it's hard to tell how successful they are, but there are some benchmarks https://github.com/EntityFX/anybench/blob/master/results/e2k_compare.md https://github.com/EntityFX/anybench/blob/master/results/e2k...

MayeulC 6y ago

> On a large die you could (theoretically) today fit say one million Motorola 68000 Processors. If you clocked that at 5Ghz it would in theory be about 1000 times faster then a Ryzen 7 using the same power. Right. Then, you have to consider how to supply power to all these transistors switching at once, which would well be in the ~10-100A range and beyond. So you have to figure out how not to have it melt (dark silicon, chiplets to have a lower power/area ratio, etc). And once you have it not melt, you have to figure out a way of making it useful: keeping the processors fed with data. Because even the algorithms that crunch just a few variables need to be supplied with those, as well as instructions, etc. This ends up sucking a lot of energy, when you have to clock long lines at 5GHz times the number of CPUs times bus width (you can trade hertz for bus width). To avoid this, we use caches. Good luck keeping your CPU count at 1M with the area SRAM needs. AMD GPUs have been memory bandwidth-starved for a few years now, their latest generation features a whooping 128MB cache. Adiabatic/reversible computing is another way to get around that, but we're not there yet, and isn't a silver bullet either. Von neumann architectures is the thing that doesn't scale. In my opinion, we are going to go back to specialized computing, especially since Moore's Law left us in the cold a few years ago. And RISC-V is quite extensible, which makes it relatively suitable for specialized architectures.

quelsolaar 6y ago
You are right, I'm simplifying a lot. I'm ignoring all kinds of issues like how all one million cores would communicate with memory or each other. I hope it at least illustrates that Perfomance / per watt is nice, but unless the perfomance is good enough to be ballpark where you need it, it doesnt matter too much. If there was a dual core CPU where each core ran twice as fast as the fastest Intel/AMD core at the same Watt as an 8 Core Intel/AMD CPU, It would sell like hot cakes, even if it was half the Performance per Watt.

toasted_flakes 6y ago

> yes, that's technically true Not even in this case, the performance and energy numbers they got for CoreMark on the M1 are off by an order of magnitude