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Xilinx-Samsung SmartSSD Computational Storage Drive Launched
- The_rationalist 6y agoSo no mention of syCL support... Only offering ~C in 2020 is an insult to computer science. Unrelated: when will Nvidia allow to seamlessly offload Java or another GC based language to the GPU? https://developer.nvidia.com/blog/grcuda-a-polyglot-language-binding-for-cuda-in-graalvm/ https://developer.nvidia.com/blog/grcuda-a-polyglot-language... GrCuda seems promising but it would only allow interoperability with Java on the CPU, not offload Java to the GPU, right? Such advances would make gpu computing order of magnitudes more developper friendly and therefore much more mainstream.
- mikewarot 6y agoXilinx makes FPGAs, not GPUs. The advantage of an FPGA is that all operations take place at the same time in hardware. Verilog is one language that I would expect strong support for... they do mention RTL, which does many of the same things. This is not a general purpose programming environment, it is more of an data flow / filtering system. There is no allocation of memory, thus no need for garbage collection.
- iron2disulfide 6y agoVerilog, VHDL, and SystemVerilog are supported by Vivado. A small subset of C++ is supported through Vivado's high level synthesis compiler, which transforms some C++ code into Verilog. RTL stands for register-transfer level, which is a general layer of abstraction; one uses a hardware description language such as Verilog to describe RTL designs. The analogy of Verilog with RTL is "Verilog is to RTL, as Haskell is to functional programming".
- teleforce 6y agoAMD owns Xilinx now, so there's that. If AMD can get their act together by seamlessly integrating their GPU, FPGA and CPU with minimum I/O bottleneck it will be a huge boon for the computing industry. People will start doing something that probably unthinkable now but will be very obvious in the near future. Personally I have one application in need of the proper integration of their disparate systems and already started talking to their R&D engineers but see little improvement being implemented. FYI, AMD has come up with SSD storage and GPU integration before but with limited success [1], but if they can also integrate FPGA together that can probably be a recipe for a great success. I think AMD and Intel (since they both own GPU/CPU/FPGA technology) really need to come up with open and intuitive design tools for these new systems or just sponsor the work on MLIR and LLHD by LLVM and ETH Zurich, respectively. [1] https://www.extremetech.com/extreme/232416-amd-announces-new-ssg-a-gpu-with-1tb-of-ssd-storage-attached https://www.extremetech.com/extreme/232416-amd-announces-new...
- cpgxiii 6y agoFPGA vendor support for higher-level synthesis tools is still pretty poor. Not surprised on that front. Offload-from-GC runtime tools do exist, e.x. Cudafy would translate .Net code into Cuda kernels and handle kernel dispatch. Of course, you were very limited in what constructs and types you could put in kernel functions, but you could write your whole application in C# and accelerate the important blocks. In practice, a lot of beginner GPU computing has moved to the world of NN training and inference, in which the complexities of GPU offload are entirely wrapped by the libraries you use. For traditional GPU-accelerated tasks, the limited languages available are not the problem. Decomposing your problem into a form that is amenable to GPU offload can be difficult, and if you're experienced enough to do that well, writing Cuda kernels and dispatch in C++ is not an obstacle. For example, Cudafy meant you didn't need to know Cuda-specific syntax and expressions, but you still had to understand the behavior and limitations of GPUs to write performant code.
- pkaye 6y agoWhat does syCL have to do with FPGAs?
- nl 6y ago> when will Nvidia allow to seamlessly offload Java or another GC based language to the GPU? Lots of garbage collected languages seamlessly target GPUs. This is typically done at the library level, either within the language ecosystem (eg in Python using Cupy instead of Numpy: https://towardsdatascience.com/heres-how-to-use-cupy-to-make-numpy-700x-faster-4b920dda1f56 https://towardsdatascience.com/heres-how-to-use-cupy-to-make...) or below it (using cuBLAS as your BLAS implementation: https://developer.nvidia.com/cublas https://developer.nvidia.com/cublas) Java can do this too - something like ArrayFire is reasonably popular: https://developer.nvidia.com/arrayfire https://developer.nvidia.com/arrayfire
- jdsully 6y agoStorage is starting to get extremely exciting again. The KV SSD's, this, and Intel's Optane are opening up a lot of new avenues for extremely high performance storage.
- UncleOxidant 6y agoDidn't Intel just sell off it's SSD division to SK Hynix?
- ohples 6y agoOptane wasn't part of the sale https://uk.reuters.com/article/intel-divestiture-sk-hynix/south-koreas-sk-hynix-to-buy-intels-nand-business-for-9-billion-idUSKBN27507T https://uk.reuters.com/article/intel-divestiture-sk-hynix/so...
- jeffbee 6y agoThey should have called it OINF: OINF is not flash.
- mikewarot 6y agoI have a 1,000,000,000 byte file on my Optane SSD, and it loads into RAM in about 4 seconds, with zero tweaking, under Windows. The thing is wicked fast, even on a consumer laptop. Intel didn't sell the best of their SSD tech, just the lower end stuff.
- jlundberg 6y agoCurious, but 1 GB in four seconds sounds kind of slow?
- sudosysgen 6y agoIsn't that slower than a lot of SSDs? Mine can do that in around 2 and a half seconds and it's not Optane, just a normal NVMe SSD.
- 6y ago
- sitkack 6y agoThis is super exciting. It makes no mention of on device bandwidth.
- wtallis 6y agoOn-device bandwidth is PCIe 3 x4 (~3.5GB/s full duplex). The FPGA is separate from the SSD controller, which is an off the shelf Samsung controller. A portion of the FPGA's resources are used as a PCIe switch: the FPGA is connected to the host PCIe link and presents one PCIe endpoint for the FPGA and one for the SSD that is connected through the FPGA. Other companies in the computational storage area are putting compute resources onto their SSD controller ASICs so that the compute doesn't have a PCIe bottleneck between it and the NAND. But you won't see that kind of design coming out of a Samsung/Xilinx collaboration.
- sitkack 6y agoIf these drives are just fpgas sitting on the existing interface, so still hitting the PCIe limits, then this is un-impressive. If we start seeing multiples of device bandwidth available to the FPGA, then we can see huge cost savings.
- wtallis 6y agoI agree that on its own, it doesn't seem too interesting for the FPGA to be accessing the flash through the same PCIe x4 interface that the host system could use. But servers with 24+ NVMe SSDs don't always have the bandwidth to saturate all the SSDs simultaneously; they're often connected through a PCIe fanout switch that has just an x16 uplink (or an x16 per CPU socket). Having an accelerator to offload eg. search means the drives in aggregate don't have to send as much data up to the CPUs (or NICs). Even if these drives have what appears to be a sub-optimal design, they can still help alleviate bottlenecks elsewhere.
- dave_4_bagels 6y agoI'm still waiting to become skilled enough or end up invested in a project enough to merit dedicated super fast SSD storage, or some kind of exotic storage appliance!
- m3kw9 6y agoSo one can look at the chip on beside the storage as an cpu offload built inside the drive, instead of a coprocessor on the motherboard. I’m not seeing a huge use case here except the narrowest of uses like decryption, compression.
- RickHull 6y ago> except the narrowest of uses like decryption, compression These seem like broad use cases to me. Also consider ETL and database applications. Time series, finance, machine learning, search engines. It seems like the primary benefit is in terms of latency and minimizing data bussed to the main CPU.
- pfortuny 6y agoConvolution on stored data. This is huge and really really simple to implement. You could work with TB of data without the gpu. Or am I missing sometjing obvious?
- mbreese 6y agoBut, one potential issue here is that your FPGA now needs to modify the filesystem to write any new results. Maybe the use-case here is more like transforming the data on the fly. Let's say storing the data compressed, but reading it back uncompressed. This could effectively be transparent to the host CPU, but handled by the FPGA. The more that I think about it, this data flow sounds significantly more reasonable than asynchronously processing data. Then you could still read / transform / write the new data to the SSD, but you'd limit the main CPU to only sending the read/write IO, instead of the transparent transformation.
- pfortuny 6y agoI see, thanks for the explanation.
- baybal2 6y ago> I’m not seeing a huge use case here except the narrowest of uses like decryption, compression. SSD already have all provisions for both, and do it. Something like that will genuinely benefit more from a highly optimised ASIC than anything else. The use case is obviously huge, and you don't see the elephant in the room: money. Putting all those drives to even a cheapest Xeon around, increases the price n-fold over the price of the flash, unless you talk about multi-terabyte scale SSDs.
- mikewarot 6y agoI've been strongly interested in computational fabrics for at least 15 years... this looks interesting, but very, very locked down. It is my understanding that FPGA vendors have fought the open source community every step of the way. I would hate to see the future of computing locked up in a new spiffy prison.
- rjsw 6y agoIn what way is it locked down ? I guess the FPGA may be big enough that it isn't covered by the free version of the Vivado toolchain.
- saagarjha 6y agoIsn’t Vivado entirely proprietary?
- rjsw 6y agoHow does that prevent you from making use of the product described in the article ?
- saagarjha 6y agoThat comment was made in the context of a thread about open source FPGA development tools.
- rjsw 6y agoAnd I'm questioning whether lack of open source FPGA development tools means that the device is "locked down". You can do everything that the device is designed to be able to do.
- rowanG077 6y agoThat's true for any locked down device. An iPhone can do everything it is designed to do yet it could also do so much more if it weren't locked down.
- mrfusion 6y agoWould anyone want to do an explain-like-I’m-in-high-school on this?
- Wistar 6y agoMe, too. I'd like to know if these will have a practical impact on, say, media-storage for editing.
- mikewarot 6y agoThis is a new class of devices that couples fast SSD storage directly with an FPGA. The types of computing that can be done in an FPGA require a new style of programming, because in an FPGA, programs get mapped into hardware, such that data flows through the chip, with all of the code running at the same time, instead of in sequence. There are large differences in the style of programming required to get efficient use out of an FPGA... there are some ways of translating C that work, but they are crude crutches at best. This is like going back to the early days of computing, when the new machines were expensive, but very fast... and programmer time was relatively cheap. It's going to take a special new breed of programmer to make this really work well. We're at the beginning of a new era. I hope that makes sense.
- dumbfounder 6y agoIs this to be leveraged at the application level or the OS level? Since so much of the world is going to the cloud, the only applications I can think are for file systems or databases, what else is there? Is there a significant advantage for personal computers?
- mikewarot 6y agoI don't really know what this would be good for on a personal computing level. I'd do a lot of things with digital signal processing. If you had a large set of videos, and you wanted to stream a down-sampled version on the fly, the FPGA could do that type of thing, easy peasy. We're at the stage where there is maximum possibility, and minimal legacy to worry about... like the early days of the PC.
- generalizations 6y agoSorry if I missed it, but I'm not seeing it: what's the bandwidth here? i.e., the time to read, process and write back the whole contents of the disk (using just the FPGA)?
- pmorici 6y agoThis doesn’t change anything about the speed of the nvme drive it offloads the work load from the processor.
- generalizations 6y agoI was wondering about the speed at which the FPGA could read from the attached storage; the bandwidth internal to the drive.
- Severian 6y agoSo I'm thinking Deduplication on drive will be the big thing here. Think XFS or ReFS block cloning but without server side processing.
- bob1029 6y agoI think putting something like SQLite on the actual storage device could be a super efficient way to directly express your intent to the actual durable storage system and bypass mountains of virtual bullshit. The optimization opportunities are pretty obvious to me. Imagine if SQLite journaling was aware of how long the supercapacitor in the SSD would last, potentially even with real-time monitoring of device variables. You could have your entire WAL sitting in DRAM on the drive as long as it has enough stored energy to flush to NAND upon external power loss.
- jleahy 6y agoAll great, then you need to port it to something other than that one specific SSD and it's too much work. We have abstraction boundaries for a reason, we give up a small % of performance and in return we can write code once (say SQLite) and use it in many scenarios. For something like SQLite it means it's been around for a long time and had a lot of optimization work done on it (and that probably outweighs the few % gain you might get from such tight integration). You'd probably get a bigger performance gain from just not using SQL (eg. a DBM).
- wtallis 6y agoThere are really only two FPGA vendors that can compete in this space, and Xilinx is the one that's clearly ahead for computational storage applications. They already provide a platform for storage accelerator IP to be shared between this Smart SSD and their pre-existing PCIe FPGA cards that connect to standard SSDs over PCIe or networks. So porting to another accelerator platform probably isn't as big an issue as you expect. The bigger challenge I see for implementing something like SQLite on a SmartSSD is that you really don't want your database to exist on just one drive, so you need to figure out how to do HA across multiple SSDs while still offloading most of the computationally expensive database operations to the FPGAs instead of leaving it on the CPU. I think this will condemn SmartSSDs to always working at a slightly lower abstraction layer than what the application really wants.
- javajosh 6y ago
- ChuckMcM 6y agoThe core concept that you ship computation to data rather than the other way around is what made Google so impressive when it launched. There are lots of algorithms that do well in that model. Back when I was at NetApp I did a design of a system where the "smart storage" essentially labeled blocks with an MD5 hash when you went to store them. That allowed you to rapidly determine if you already had the block stored and could safely toss the one being written[1]. Really fast de-duplication and good storage compression. At Blekko they had taken this concept to the next logical step and built a storage array out of triply replicated blocks (called 'buckets') that were distributed by their hashid. You could then write templated perl code that operated in parallel over hundreds (or thousands) of buckets and giving a composite result. It always surprised me that IBM didn't care about that system when they acquired Blekko, it was pretty cool. If you implemented it in these Samsung drives it would make for a killer data science appliance. That design almost writes itself. Also in the storage space, there was the CMU "Active disk" architecture[2] which was supposed to replace RAID. There was a startup spin-off from this work but I cannot recall its name anymore, sigh. These days it would useful to design a simulator for systems like this and derive a calculus for analyzing their performance with respect to other architectures. Probably a masters thesis and maybe a PhD or two in that work. [1] Yes MD5 hash collisions are a thing but not for identical length documents (aka an 8K block), and yes NetApp got a patent issued for it. [2] https://www.pdl.cmu.edu/PDL-FTP/Active/ActiveDisksBerkeley98.pdf https://www.pdl.cmu.edu/PDL-FTP/Active/ActiveDisksBerkeley98...
- 2sk21 6y agoWasn't this the aim of Hadoop as well? Also, to be fair, IBM wasn't able to do much with any of the companies they acquired in the same timeframe as Blekko. I was working at IBM at that time and witnessed this first hand.
- ChuckMcM 6y agoI kind of gathered that IBM had this sort of love/hate relationship with acquisitions. They loved the "new ideas" but many of the "old guard" hated the idea that something from outside of IBM was novel and worth pursuing. I watched first hand as things that had been done by a company that was acquired were buried while the exact same kind of thing done by IBM research was given lots of funding. I understood not having two efforts, but suggested they be blended to get the best of both teams, alas that was shot down. At one time IBM research had a pretty awesome storage group, perhaps they will will have a computational storage fabric offering at some point.
- jmpman 6y agoToo bad IBM killed off Netezza. If the cloud vendors started offering this widely, it would have given them another round of relevance.
- foobiekr 6y agoI wonder how hard it would be to port the server-side code of FoundationDB to one of these devices; architecturally FDB seems well suidted to this (at least until predicates show up) as it is already extremely constrained as to the expectations on the storage nodes; they basically provide just (time-bounded) versioned KV access.
- rkagerer 6y agoCan anyone quantify the advantages this yields in terms of latency and bandwidth, compared to plugging a regular SSD into an external FPGA (via PCIe or whatever interface)?
- avmich 6y agoReminds me of Micron's Automata Processor: https://www.cs.virginia.edu/~skadron/Papers/wang_APoverview_CODES16.pdf https://www.cs.virginia.edu/~skadron/Papers/wang_APoverview_...
- ze_m 6y agoThat reminds me of calculating the mandelbrot set on the commodore 1541 floppy drive, back in the days.
- Taniwha 6y agoLooks like this is a Xylinx KU15P - not shabby, but about 1/2 the size of the 3-die monstrosities that are in the AWS FPGA instances you can rent for ~$1.50 an hour - so useful for disk stuff closely coupled to the drive, but maybe not as a general compute resource (depending on actual price of course)
- gfody 6y agoThey really should extend KVS for this - it's going to be very difficult to leverage if the XSS interface is underneath the filesystem (as shown in the diagram) especially for RDBMS where the database is (usually) a single big flat file as far as the filesystem is concerned.
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