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Apple’s A14 Packs 134M Transistors/mm²
- pwinnski 6y ago"A14 comes in at a cool 78% effective transistor density when compared to theoretical density." Wowsers. Apparently SRAM is the limiting factor.
- jhloa2 6y agoIf SRAM is as ubiquitous throughout chip designs as the article suggests, wouldn't that mean the theoretical density prediction is off?
- Symmetry 6y agoTime for eDRAM! Ok, this process doesn't support eDRAM. Also, I don't understand the SRAM scaling failure here and I don't know if it would apply to eDRAM too. But it's something to think about given the increasing importance of wire delay.
- FullyFunctional 6y agoI'm not sure you are serious, but eDRAM isn't a direct replacement for SRAM. At best it's useful for L3 or L4 cache given the inherently higher latencies. I think we just have to accept that silicon scaling is slowing down.
- Symmetry 6y agoI was assuming last level cache would be the majority of the usage in this case. Maybe I'm wrong.
- FullyFunctional 6y agoFor a desktop CPU that wouldn't be far off, but the A14 has a lot of other stuff so I very much doubt that. However, until we see an actual floor plan this is all speculation.
- my123 6y agoOn the recent IBM z processors, eDRAM is used even for the L1 chip. And that's above 5GHz.
- FullyFunctional 6y agoThanks, I stand corrected! Isn't eDRAM an IBM-only technology?
- callesgg 6y agoThe theoretical maximum density is probably based on some type of physical law or just a simplified model. That is often what people talk about when they talk about theoretical maximums/minimums. Like if you have a box of dimensions 10x10x10cm the theoretical maximum number of dice of dimension 1x1x1cm you can fit in the box is 1000 dices. Chances are you won’t get 1000 dices in to the box as the world is more complex than the theoretical model we used for the scenario.
- ineedasername 6y agoWhich is why if you want to build a box that holds 1000 dice, you need to take into account the +/- tolerances in your build process. At a guess, you'd probably want to build at something like [dimensions] + 2*[tolerance]. So if your build process produced a 10cm cube with +/- 1mm, you'd want to build a 10.2mm cube so even a worse-case -1mm tolerance issue you'd still have +1mm of and so still be able to get the dice in without using force. And assuming the dice themselves didn't have some crazy high tolerance ranges. I've got a side-gig/hobby making stuff, and the the 2x tolerance works pretty well as a rule of thumb for me, but the project type, material, and application probably play a big part in those considerations. Any industrial/mechanical/materials engineer care to weigh in?
- rdw 6y agoThe article says that Apple isn't making full use of the 5nm process node, and blames lack of SRAM scaling for it (presumably due to the large amount of L3 cache). Is this a problem that all processors are about to hit, or is this going to be overcome once process engineers are more familiar with 5nm?
- FullyFunctional 6y agoThey optimize SRAM far in advance of introducing the process, after all this is one of the most critical components. It's very unlikely you'll see any further SRAM improvement on this process, but a process optimization can improve it (and everything else).
- ajross 6y agoThis bit didn't make a lot of sense to me. SRAM is routinely the MOST optimized and MOST worried-over aspect of silicon layout. SRAM cell architectures get hand-optimized carefully years in advance of any process improvements. They aren't just logic that gets spit out of generic tooling. So while it would make sense that a new process would have new design rule that didn't map well to older EDA tooling, it's harder to see that argument holding for SRAM. If SRAM isn't scaling, why is general logic?
- hajile 6y ago> It can be noted that the cell size reduction rate from 2017 to 2018 to 2019 is much slower than the rate for preceding years 2011 to 2017, showing that SRAM cells have not been scaling at the same rate as logic in general. At IEDM 2019, the 5nm process was quoted to have 1.84x logic density improvement compared to 1.35x SRAM density improvement[1] 0.021um per cell [1] for TSMC N5 vs 0.027um per cell [0] for TSMC N7. Even if Apple did everything right, they'd still be behind due to the limits of the process. [0]https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/ https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells... [1]https://semiwiki.com/semiconductor-manufacturers/tsmc/283487-tsmcs-5nm-0-021um2-sram-cell-using-euv-and-high-mobility-channel-with-write-assist-at-isscc2020/ https://semiwiki.com/semiconductor-manufacturers/tsmc/283487...
- talentedcoin 6y agoI think this is cool if they’re the future of the Mac, but aren’t these chips just wasted in the iPad? I say this as an iPad Pro (1st-gen) owner ... it’s already way more processing power than I can really use, because after trying for months to get a sensible workflow going (mostly based around Pythonista, Editorial and RealVNC) I’ve relegated it to a OneNote and Netflix machine. What’s the point other than the coolness factor? Is it some future AR-type application?
- Moto7451 6y agoMy understanding from talking to friends who work at Apple and some of the product briefs is a lot of the hardware is used for video and photo processing. Video games take advantage of the extra CPU/GPU power as well. I don’t think that’s all that Apple specific as there are increased ISPs and security chips on other phones as well.
- samatman 6y agoNot if you start juggling several streams of 4k video, it's not. Also, one can play games on an iPad, and games will soak up arbitrary amounts of CPU and GPU power.
- jagged-chisel 6y agoI'm sure Apple consider the iPad Pro as a testing ground for these chips.
- kitotik 6y agoAudio and Video work will take all the transistors you can throw at it. Things like GarageBand and 3rd party software synthesizers can easily max out even latest gen iPad Pros. Not to mention games…
- Cookingboy 6y ago>What’s the point other than the coolness factor? So Genshin Impact can look and run beautifully XD
- manmal 6y agoHaving a more-powerful-than-necessary CPU has many benefits, here are some: - Less heat produced > allows for smaller heatsinks and, as a result, smaller devices or bigger components - Performance bottlenecks become less likely - Features like 120hz display refresh rate become possible without the user noticing degradation - Faster OS boot and app starts - Ability to do more work locally vs using a server (see the many ML features) - Tech debt in system code is less of an issue - code can be shipped early and optimized later
- exabrial 6y agoFor comparison I was trying to nail down what Intel's 7nm process is, but I've found answers between 120nm and 215nm. If anyone knows, that'd be an interesting comparison.
- kop316 6y agoConsidering this news: https://finance.yahoo.com/news/intel-now-ordering-chips-tsmc-072255657.html https://finance.yahoo.com/news/intel-now-ordering-chips-tsmc... I sincerely doubt Intel will ever disclose it.
- wmf 6y agoIntel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 million transistors per square millimeter. https://en.wikichip.org/wiki/7_nm_lithography_process#P1276 https://en.wikichip.org/wiki/7_nm_lithography_process#P1276
- tpmx 6y agoFoundry sale price of $238/chip seems way too high. See e.g. https://www.cultofmac.com/658650/iphone-11-pro-max-production-cost-bill-materials-bom/ https://www.cultofmac.com/658650/iphone-11-pro-max-productio... > Apple A13 processor that (is) supposedly is priced at $64.
- grenoire 6y agoSomebody has to do it and Apple has the cash, I think they can afford to.
- samatman 6y agoThat is apparently the price to assure that Apple is the only purveyor in town with a 5nm process chip. Worth it? Apple thinks so.
- wmf 6y agoApple doesn't have an exclusive on 5 nm; it's also being used by Kirin 9000, Snapdragon 875, some Exynos, and a future Dimensity SoC.
- samatman 6y agoI'm not sure how to square that claim with this sort of article: https://www.extremetech.com/computing/315186-apple-books-tsmcs-entire-5nm-production-capability https://www.extremetech.com/computing/315186-apple-books-tsm...
- SSLy 6y agoI believe it's about the remaining fab capacity that was available at that time
- grandmczeb 6y agoSnapdragon 875 is 5nm, but on Samsung's process not TSMC's[1]. [1] https://www.techpowerup.com/272139/samsung-foundry-to-become-sole-manufacturer-of-qualcomm-snapdragon-875-on-5-nm-euv-manufacturing-process https://www.techpowerup.com/272139/samsung-foundry-to-become...
- tpowell 6y agoI was curious just how many chips per wafer they net. From this 2018 article[1], it appears to be ~530 at 5nm, which would be $32ea if that yield is accurate. The same article estimated 7nm chips came out to $18ea. Apparently, R&D spend went up 50% from 7nm to 5nm. I'm curious to see how many flavors of the A14 Apple cooks up given the comparatively high die cost. [1] https://wccftech.com/apple-5nm-3nm-cost-transistors/ https://wccftech.com/apple-5nm-3nm-cost-transistors/
- wincy 6y agoThis might be one of the reasons they're transitioning to Apple Silicon, as it will allow them to justify the raising R&D costs over a wider array of products.
- macintux 6y agoAre Mac volume numbers even a rounding error relative to mobile devices?
- saagarjha 6y agoMac sales by volume are about 10% of iPhone sales.
- sjwright 6y agoWhile 10% is small in relative terms, it's still huge in absolute terms. And the Mac also remains an important nexus for Apple's wider ecosystem, even if a significant majority of their customers will never own one. Because of the way Apple technology is developed, and by virtue of being largely untethered and unmanaged, Mac is the bootstrap platform for everything else Apple does. It doesn't always have to be so, but I don't see Apple releasing anything else which could take its place.
- ineedasername 6y agoI thought it was also interesting that cost-per-transistor had remained the same as well.
- topspin 6y agoI really appreciate this analysis and the straightforward top line number 134e6/mm^2. The usual "node" figure is utterly meaningless; an electrical engineer couldn't care less about "feature" size (whatever that means.) What is the count of discrete components in a given area? There are 40 billion 5nm (the supposed "node" of these chips) squares in a millimeter of area. That's two orders of magnitude more dense than 134 million. The meaningful achievement is how many discrete electrical components are composed into a given area. Not some arbitrary dimension of some cherry picked subset of these components.
- moonchild 6y ago> The meaningful achievement is how many discrete electrical components are composed into a given area. Not some arbitrary dimension of some cherry picked subset of these components. I disagree. The meaningful achievement is how power-efficient, fast, and cheap you can make a given chip. (Secondarily, how small and how durable wrt cosmic rays; but for most purposes these are not super important.) If that follows as a result of many discrete electrical components being packed into a small area, great; but the latter isn't intrinsically interesting.
- topspin 6y ago> If that follows Efficiency, performance and cost are strongly related to density. Price less so; that's a function of supply and demand.
- asdfasgasdgasdg 6y ago> Efficiency, performance and cost are strongly related to density. Price less so; that's a function of supply and demand. They are related, of course, but the important stuff can be measured more directly by looking at how well programs work on a given computer. I think it's just a little odd to praise one cherry-picked, arbitrary metric for being less game-able than another cherry-picked, arbitrary metric. Especially when we have metrics to hand that are a lot closer to what real people care about in a computer. I certainly have never shopped for a CPU based on the number of transistors, but I have made purchasing decisions based on things like cinebench and passmark scores, which try to get at what ultimately matters to me (i.e. how many FPS a CPU will drive in the games I play).
- ineedasername 6y agoWhat's the relative heat dissipation between logic & SRAM on a chip? The article talks about layering as a potential way forward for SRAM, but that would come with more complex TDP management, unless SRAM isn't burning watts at the same rate as the rest of the chip.
- Tuna-Fish 6y agoSRAM can potentially use very little power on modern processes, depending on how fast you want to be able to access it. If you are just making a relatively low-speed L3, getting rid of the heat produced in the SRAM itself will never be a problem. In general, the problem in SRAM layered on chip is considered to be that the stacked dies are a very good insulator, so the hot active die on the bottom will have heat dissipation problems.
- Symmetry 6y agoThere's also smaller, but less efficient and slower 6 transistors cells versus larger but more efficient and faster 8 transistor cells to compare.
- nimish 6y agoThis is about 35% denser than intel 10nm, and not a theoretical number.
- baron816 6y agoWould hate to be the guy that had to count all those transistors.
- microtherion 6y agoIt's not that hard: You just count the pins and divide by 3.
- m463 6y ago"As of 2019, the highest transistor count in any IC chip is Samsung's 1 TB eUFS (3D-stacked) V-NAND flash memory chip, with 2 trillion floating-gate MOSFETs (4 bits per transistor)." At 4 bits per transistor and 3 pins, how do you count the samsung bits? :)
- Buraksr 6y agoThe trick is mixing in some good ol analog, and having 2^4 voltages that can be loaded and stored in each transistor
- ChuckMcM 6y agoI found this to be a pretty confusing article. I get that they are analyzing the new node, which is great, but the editorializing seems a bit premature to me. I also don't think the author understood the TMSC presentation. TMSC clearly said that is used a "model" of a typical SOC of 60% logic, 30% SRAM, and 10% analog. Then they said that for each category of thing, you could expect 1.8x, 1.35x, and 1.2x of shrink. If you do the math, that means an overall shrink for a 'typical' SOC that conforms to their model would be 1.57x (approximately). That Apple achieved 1.49x would suggest they got 95% of the process shrink effectiveness. Then there is the cost per die and thus cost per transistor discussion. It is important to remember that this is likely the most expensive these wafers will ever be. The reasoning for that statement is that during a process node life-cycle the cost per wafer is set initially to capture "early movers" (who value density over cost). Much like any product where competition will emerge "later" there is a window early on to recapture value which can pay back your R&D and capital equipment investments. As a result the vendor sets the price as high as possible to make that repayment happen as quickly as possible. Once paid back, the price provides profit as long as it can be supported in the presence of other competitors (in this case, I would guess that role is played by Samsung). The GSA uses to publish price surveys of wafers on various nodes over time but they don't seem to do that any more. Anyway, so the cost per transistor will go down from this point but how much depends on how much margin is in the current wafer price. So I agree that the cost per transistor is not going down as quickly as it has in the past, and its possible that this node may not get to be as low as the previous node. I'm curious how it compares when you look at 7nm introduction price per transistor vs todays price per transistor. And if you get the same ramp with the 5nm node what that would mean.
- thornjm 6y agoThe column is explicitly labelled "effective vs theoretical" though. There is nothing misleading there.
- ChuckMcM 6y agoThis is where I believe the author goes astray: "Despite TSMC claiming a 1.8x shrink for N5, Apple only achieves a 1.49x shrink." TSMC does NOT say they have a 1.8x shrink for N5, they say for LOGIC you can get that, but for SRAM and Analog the results are 1.35x and 1.2x. Had they summed that together for a "typical SOC", which they also discuss (and one presumes that Apple makes typical SOCs) then the "theoretical" shrink is 1.57x for SoCs. The challenge is that whereas at one time the node size was that of a "gate" (which could be 4 transistors), in a marketing race for smaller numbers fabs started emphasizing "feature" size. Because of this change, the "theoretical shrink" is a function of what kinds of circuits you're putting down. Pure logic? You get one number, two gates connected together for a flip-flop, you get another number, a voltage regulator, or ADC filter, you get another number. So doing the analysis the author claims to do, can ONLY be done if you know what percentage of the part you are making on the new process is what. I am under the impression that they missed that.
- fuck_red_china 6y agoThat's roughly 3.4B transistors/in^2
- amelius 6y agoIsn't this mostly TSMC's achievement? Can't their other clients reach the same density?
- Buraksr 6y agoYes and no. TSMC's process node gives some hard upper limit to what can be built, but whether you can make your design that compact is an open question. One consideration is that while we think of each transistor as individual and isolated, in reality they are simply wells of n and p type silicon with some oxides and metal thrown in. Because of this we can get unwanted parasitic components and latches. A BJT transistor for example is just a pattern of three silicon types, so it is somewhat inevitable that these will occur, whether they cause issues, and to what extent depends on the design. Packing everything as tight as possible gives noise concerns, thermal concerns, signal integrity issues ect. This is not to devalue the achievement of TSMC, but to state that design work is still a work as well. [1] https://ieeexplore.ieee.org/document/145696 https://ieeexplore.ieee.org/document/145696
- amelius 6y agoOk, but doesn't Apple use EDA tools for that? Or did they develop their own?
- jagger27 6y agoI was curious and looked up how this compared to the computer my family had 20 years ago: a Dell XPS tower with a Pentium III. The A14 has more than 1,000x as many transistors as what Intel was doing 20 years ago on a 128mm^2 die. Pretty incredible.
- toddmatthews 6y agoHad that same computer when I was a senior in high school 1999
- hmottestad 6y agoAs someone with an 8 year old MacBook Pro that isn’t all that much slower than my 2019 16”.... I am so glad Apple is still pushing the envelope. Back in the old days we used to get a doubling of performance every year or two. Then Intel got into trouble and has been producing the same chips for what 4-5 years? Essentially just minor changes. It’s not really Apple’s fault that the rest of the industry is lagging so badly on performance. My Nokia was fast enough, of course no one “needs” a faster phone. But it only appears so much faster because the rest of the industry has stagnated. Had Intel kept their tick-tock cadence then these new "faster” phones would hardly be considered fast.
- titzer 6y agoBlaming Intel for the end to frequency scaling is overblown. The reality is that the entire field started to hit limitations imposed by physics on the current silicon trajectory. While transistors kept (and keep) getting smaller, it's diminishing returns squeezing clockspeed and single-core performance out of it. Instead, everything has been going into scaling horizontally with more cores and more cache.
- hmottestad 6y agoThe A14 scores 50% higher single core performance in geekbench compared to the i7 in my 16”MacBook Pro from 2019. Also the current gen high end laptop CPUs from Intel are still 14nm. Which they introduced in 2015 with broadwell [1]. Others have shown that’s it’s very possible to scale beyond 14nm, so there is good reason to blame Intel here! 1. https://ark.intel.com/content/www/us/en/ark/products/87719/intel-core-i7-5850hq-processor-6m-cache-up-to-3-60-ghz.html https://ark.intel.com/content/www/us/en/ark/products/87719/i...
- raydev 6y agoMy 2013 high end 15" MBP gets pretty hot when I'm watching 1080p or higher videos. Chrome+YouTube is even worse, it even drops frames. Compiling Swift is even worse than that. I have a work-provided 16" MBP that does all these things effortlessly.
- throwaway4good 6y agoFor comparison. The Kirin 9000 (which includes a 5G modem) appears to have 15.3B transistors, the A14 has 11.8B transistors. https://en.wikipedia.org/wiki/Transistor_count https://en.wikipedia.org/wiki/Transistor_count Has a big table listing a number of historical CPUs.
- hellokaushik 6y agoNice