7 ms·

Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics ba

by jmt_ 6y ago

Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?

vkou 6y ago
It's easy. You take a very small number, add the letters 'nm' to it, and then start sending out press-releases to the major media outlets. That number has nearly zero bearing on the actual physical sizes of the chip's components. The only people who know about the exact dimensions are the firms placing manufacturing contracts with TSMC.
- vmception 6y ago
  You get it
- gruez 6y ago
  >That number has nearly zero bearing on the actual physical sizes of the chip's components. AFAIK the reason behind this madness is that the number previously did correspond to feature size, but then they discovered methods of increasing transistor density without decreasing the size of the components. Since the feature size was used in marketing as a proxy for transistor density, they felt it was ultimately justified to decrease the number. After all, if your enhanced 32nm process provided the same transistor density as your competitor's 22nm process, why shouldn't you market your process as "22nm"?
  - egsmi 6y ago
    That number used to set the scale for the design rule set. https://www.electronics-tutorial.net/Digital-CMOS-Design/CMOS-Layout-Design/CMOS-lambda-Design-Rules/ https://www.electronics-tutorial.net/Digital-CMOS-Design/CMO...
nicoburns 6y ago
To make an analogy: I think a good way to think about it is that the 7nm node doesn't actually produce chips with 7nm features, it uses a "knife" (actually it's a lithography process) which is able to cut things as small as 7nm . That enables it to be more precise than a bigger "knife" so even though the size of the chip features is >7nm they are still able to be smaller than features cut with a 10nm "knife". I don't actually know anything about chip production. But that's what I've picked up from HN.
- tux3 6y ago
  One thing people are trying to convery every time this question comes up is that "7nm" is really just a marketing number, it's not tied to any particular physical dimension, and it's not how small the knife is able to cut. The knife does get better, it's just not something that the Xnm node names measure directly.
- marcosdumay 6y ago
  That's kinda the idea. There are also several different layers each with its own resolution. Also, well, that number isn't really the actual resolution of the finest layer, but is some "marketing processed" message that should give you an idea of the chips performance. It used to have the meaning you stated, but things changed a while ago.
Nokinside 6y ago
The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation. The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name. They are not even comparable across companies. For example, TSMC 7nm process technology has 91 MTr/mm², Intel's 10 nm prosess technology has 100 MTr/mm². Samsung 10nm has 52 MTr/mm². (MTr/mm² refers to millions of transistors per mm²).
- swiley 6y ago
  That's interesting, I saw a hobbyist photo lithography setup the other year that was able to etch metal with a resolution of 20nm.
  - phkahler 6y ago
    That's really not possible. 20um probably. Micro not nano.
    - MayeulC 6y ago
      Well, nano would be achievable via e-beam lithography, but photolithography is another beast: I'm pretty sure you need EUV at that size, with special (expensive) lenses that do not absorb the UV.
  - anon73044 6y ago
    I recall this but don't remember seeing anything smaller being posted. Sub 100nm for a hobbiest would be pretty awesome. https://youtu.be/YAPt_DcWAvw https://youtu.be/YAPt_DcWAvw
  - imtringued 6y ago
    State of the art non EUV photo lithography uses light with a 193 nm wavelength. 20nm is significantly below that which would imply usage of highly advanced lithography techniques like multiple patterning. A chip manufactured with a 20nm resolution would involve dozens of masks which were created through electron-beam lithography. Just the mask set alone would cost millions of dollars. The only hobbyist that I am aware of used a pretty nifty mask less technique but the resolution doesn't come close at all. I think you just mixed up your units.
robert_dipaolo 6y ago
der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting; https://youtu.be/uEMDkbF3hu0 https://youtu.be/uEMDkbF3hu0 https://youtu.be/uXu_1zXOZdY https://youtu.be/uXu_1zXOZdY https://youtu.be/_wAeL3f3iV4 https://youtu.be/_wAeL3f3iV4
- agumonkey 6y ago
  With all the electronics and physics chans I binge on youtube I'm surprised this one never hit the suggestion fan, it's utterly fascinating
  - jpgvm 6y ago
    der8auer is basically the patron saint of PC overclocking, highly recommend his coverage of new hardware because he goes straight to doing interesting stuff and skips the usual review stuff that everyone else repeats.
    - agumonkey 6y ago
      I think we left the holy land of pc overclocking long ago.. this dude just showed us chemical coating of transistors.. Even Applied Science would be jealous.
1000100_1000101 6y ago
Not the explanation you're looking for, but the CTO at TSMC co-invented the modern FinFET transistor. They've probably good a really good grasp on what issues block development of smaller features, and know how to find ways around those limits. https://spectrum.ieee.org/semiconductors/devices/how-the-father-of-finfets-helped-save-moores-law https://spectrum.ieee.org/semiconductors/devices/how-the-fat...
- egsmi 6y ago
  He also wrote an excellent introduction to semiconductor physics textbook, that Berkeley hosts for free! https://www.chu.berkeley.edu/modern-semiconductor-devices-for-integrated-circuits-chenming-calvin-hu-2010/ https://www.chu.berkeley.edu/modern-semiconductor-devices-fo...
  - LargoLasskhyfv 6y ago
    Thanks!
imtringued 6y ago
The nm process numbers refer to the necessary dimensions of a theoretical planar transistor to achieve the same density as this process. Planar transistors haven't been used for at least a decade. To make matters worse there is no standardized planar transistor design so ultimately you cannot derive any meaning from these numbers other than as a fancy version number that tells you which process is newer. As many others have commented: It's much better to just look at overall transistor density. FinFET and GAA (gate all around) are 3d transistor designs. Therefore you get impossible and purely theoretical planar numbers.
rasz 6y ago
der8auer "14nm and 7nm are NOT what you think it is - Visiting Tescan" https://www.youtube.com/watch?v=1kQUXpZpLXI https://www.youtube.com/watch?v=1kQUXpZpLXI for reference "TESCAN is a leading global producer and supplier of scanning electron microscopes, focused ion beam scanning electron microscopes and micro-CT solutions."

by jmt_ 6y ago

vkou 6y ago

It's easy. You take a very small number, add the letters 'nm' to it, and then start sending out press-releases to the major media outlets. That number has nearly zero bearing on the actual physical sizes of the chip's components. The only people who know about the exact dimensions are the firms placing manufacturing contracts with TSMC.

vmception 6y ago
You get it
gruez 6y ago
>That number has nearly zero bearing on the actual physical sizes of the chip's components. AFAIK the reason behind this madness is that the number previously did correspond to feature size, but then they discovered methods of increasing transistor density without decreasing the size of the components. Since the feature size was used in marketing as a proxy for transistor density, they felt it was ultimately justified to decrease the number. After all, if your enhanced 32nm process provided the same transistor density as your competitor's 22nm process, why shouldn't you market your process as "22nm"?
- egsmi 6y ago
  That number used to set the scale for the design rule set. https://www.electronics-tutorial.net/Digital-CMOS-Design/CMOS-Layout-Design/CMOS-lambda-Design-Rules/ https://www.electronics-tutorial.net/Digital-CMOS-Design/CMO...

nicoburns 6y ago

To make an analogy: I think a good way to think about it is that the 7nm node doesn't actually produce chips with 7nm features, it uses a "knife" (actually it's a lithography process) which is able to cut things as small as 7nm . That enables it to be more precise than a bigger "knife" so even though the size of the chip features is >7nm they are still able to be smaller than features cut with a 10nm "knife". I don't actually know anything about chip production. But that's what I've picked up from HN.

tux3 6y ago
One thing people are trying to convery every time this question comes up is that "7nm" is really just a marketing number, it's not tied to any particular physical dimension, and it's not how small the knife is able to cut. The knife does get better, it's just not something that the Xnm node names measure directly.
marcosdumay 6y ago
That's kinda the idea. There are also several different layers each with its own resolution. Also, well, that number isn't really the actual resolution of the finest layer, but is some "marketing processed" message that should give you an idea of the chips performance. It used to have the meaning you stated, but things changed a while ago.

Nokinside 6y ago

The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation. The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name. They are not even comparable across companies. For example, TSMC 7nm process technology has 91 MTr/mm², Intel's 10 nm prosess technology has 100 MTr/mm². Samsung 10nm has 52 MTr/mm². (MTr/mm² refers to millions of transistors per mm²).

swiley 6y ago
That's interesting, I saw a hobbyist photo lithography setup the other year that was able to etch metal with a resolution of 20nm.
- phkahler 6y ago
  That's really not possible. 20um probably. Micro not nano.
  - MayeulC 6y ago
    Well, nano would be achievable via e-beam lithography, but photolithography is another beast: I'm pretty sure you need EUV at that size, with special (expensive) lenses that do not absorb the UV.
- anon73044 6y ago
  I recall this but don't remember seeing anything smaller being posted. Sub 100nm for a hobbiest would be pretty awesome. https://youtu.be/YAPt_DcWAvw https://youtu.be/YAPt_DcWAvw
- imtringued 6y ago
  State of the art non EUV photo lithography uses light with a 193 nm wavelength. 20nm is significantly below that which would imply usage of highly advanced lithography techniques like multiple patterning. A chip manufactured with a 20nm resolution would involve dozens of masks which were created through electron-beam lithography. Just the mask set alone would cost millions of dollars. The only hobbyist that I am aware of used a pretty nifty mask less technique but the resolution doesn't come close at all. I think you just mixed up your units.

robert_dipaolo 6y ago

der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting; https://youtu.be/uEMDkbF3hu0 https://youtu.be/uEMDkbF3hu0 https://youtu.be/uXu_1zXOZdY https://youtu.be/uXu_1zXOZdY https://youtu.be/_wAeL3f3iV4 https://youtu.be/_wAeL3f3iV4

agumonkey 6y ago
With all the electronics and physics chans I binge on youtube I'm surprised this one never hit the suggestion fan, it's utterly fascinating
- jpgvm 6y ago
  der8auer is basically the patron saint of PC overclocking, highly recommend his coverage of new hardware because he goes straight to doing interesting stuff and skips the usual review stuff that everyone else repeats.
  - agumonkey 6y ago
    I think we left the holy land of pc overclocking long ago.. this dude just showed us chemical coating of transistors.. Even Applied Science would be jealous.

1000100_1000101 6y ago

Not the explanation you're looking for, but the CTO at TSMC co-invented the modern FinFET transistor. They've probably good a really good grasp on what issues block development of smaller features, and know how to find ways around those limits. https://spectrum.ieee.org/semiconductors/devices/how-the-father-of-finfets-helped-save-moores-law https://spectrum.ieee.org/semiconductors/devices/how-the-fat...

egsmi 6y ago
He also wrote an excellent introduction to semiconductor physics textbook, that Berkeley hosts for free! https://www.chu.berkeley.edu/modern-semiconductor-devices-for-integrated-circuits-chenming-calvin-hu-2010/ https://www.chu.berkeley.edu/modern-semiconductor-devices-fo...
- LargoLasskhyfv 6y ago
  Thanks!

imtringued 6y ago

The nm process numbers refer to the necessary dimensions of a theoretical planar transistor to achieve the same density as this process. Planar transistors haven't been used for at least a decade. To make matters worse there is no standardized planar transistor design so ultimately you cannot derive any meaning from these numbers other than as a fancy version number that tells you which process is newer. As many others have commented: It's much better to just look at overall transistor density. FinFET and GAA (gate all around) are 3d transistor designs. Therefore you get impossible and purely theoretical planar numbers.

rasz 6y ago

der8auer "14nm and 7nm are NOT what you think it is - Visiting Tescan" https://www.youtube.com/watch?v=1kQUXpZpLXI https://www.youtube.com/watch?v=1kQUXpZpLXI for reference "TESCAN is a leading global producer and supplier of scanning electron microscopes, focused ion beam scanning electron microscopes and micro-CT solutions."