14 ms·

TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

110 points by Nokinside 6y ago

Alopis 6y ago
With this news, how much of a lead do they have over Intel now? When is Intel realistically going to ship their next node? Or is it all still perpetually delayed with no end in sight?
j4nt4b 6y ago
So is it safe to assume that Apple will book 100% of the first production runs for this new process as well?
- vbezhenar 6y ago
  I think it depends on price. At some point chips will cost too much for consumer electronics. You wouldn't want to buy iPhone with $1000 CPU.
  - throwaway4good 6y ago
    A mass volume product like an iPhone is the only thing that generates enough money to sponsor this form of development.
    - marcosdumay 6y ago
      Yes, fabs take a large amount of risk when they develop new processes. That doesn't mean that Apple is interested. At least right now. Processes also tend to be improved with time.
  - epicureanideal 6y ago
    Sign me up!
  - mschuster91 6y ago
    > You wouldn't want to buy iPhone with $1000 CPU. 1.000 US$ no, but... I would not put it past Apple to make a literal system on chip. Like, one chip with everything on one die stack: CPU, GPU, RAM, cell modem, voltage regulators... the only external components would be ports and whatever cannot be reasonably expressed on a silicon die (e.g. coils for voltage regulators).
  - AgloeDreams 6y ago
    Chips don't really work like that. 99% of the cost is in R&D and factory development then the cost per chip is pretty low, you just have to average in the R&D cost right? Apple sells ~ 200M units every year and prior developments get rolled into low cost products. Each new process probably leads Apple to make at least 500M devices. At scale you can spend 10s of billions on R&D and be spending less than $15-25 per chip.
  - zamalek 6y ago
    Price depends on yields, and 90% is pretty damned good.
- ksec 6y ago
  It depends on a lot of factors, but mainly cost and yield. Example; Apple didn't use any 7nm EUV variant in A12/A13. While Huawei used it for their SoC. Having said that MBCFET, or more commonly known as GAA was originally scheduled for 3nm in 2022, so giving another 2 year to bake should help. So yes, if everything were executed to absolute perfection, then we should see a 2nm Apple Silicon in 2024. Note: While Wccftech has gotten a lot better in the recent 12 months or so, I still wouldn't put them into reliable and trusted source. It is good for rumours and entertainment, but that is about it. ( Personally I would rather not have it appear on HN )
throwaway4good 6y ago
Is TSMC the only who is close to doing this? What about Samsung or Intel? Or research labs that do smaller runs?
- vbezhenar 6y ago
  I think that Intel is one step behind. They'll likely produce 7nm in 2024 which should be comparable with TSMC 5nm. But TSMC 5nm already available for Apple.
  - derision 6y ago
    Intel is more like 3 steps behind, one of their shoes is missing and the other is missing laces
    - hinkley 6y ago
      Having lived inside similar but much smaller dramas, it smells to me like Intel is titrating bad news. There was a goal. The goal became PR. Someone in management began to believe the PR, and turned it into a promise, predicated on 'and then a miracle occurs' (the engineers figure out how to do some things that haven't been done before). The engineers keep trying to explain how nobody has done this before because you can't. To do so involves violating the laws of physics or Information Theory. Anyone who cracks this problem deserves a Nobel nomination, so that probably isn't us. Middle management is stuck in the middle because someone has made promises we can't keep, and they either make it worse or help cover it up by playing for time. You either solve a different problem that has similar behavior (or at least, until researchers discover Meltdown), or you slowly reset expectations until people are chronically grumpy but nobody is yelling.
      - reducesuffering 6y ago
        This exact scenario is parodied in the show Silicon Valley[0] It's probably fairly commonplace. [0] https://www.youtube.com/watch?v=QZ7m7mV864A https://www.youtube.com/watch?v=QZ7m7mV864A
jmt_ 6y ago
Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?
- vkou 6y ago
  It's easy. You take a very small number, add the letters 'nm' to it, and then start sending out press-releases to the major media outlets. That number has nearly zero bearing on the actual physical sizes of the chip's components. The only people who know about the exact dimensions are the firms placing manufacturing contracts with TSMC.
  - vmception 6y ago
    You get it
  - gruez 6y ago
    >That number has nearly zero bearing on the actual physical sizes of the chip's components. AFAIK the reason behind this madness is that the number previously did correspond to feature size, but then they discovered methods of increasing transistor density without decreasing the size of the components. Since the feature size was used in marketing as a proxy for transistor density, they felt it was ultimately justified to decrease the number. After all, if your enhanced 32nm process provided the same transistor density as your competitor's 22nm process, why shouldn't you market your process as "22nm"?
    - egsmi 6y ago
      That number used to set the scale for the design rule set. https://www.electronics-tutorial.net/Digital-CMOS-Design/CMOS-Layout-Design/CMOS-lambda-Design-Rules/ https://www.electronics-tutorial.net/Digital-CMOS-Design/CMO...
- nicoburns 6y ago
  To make an analogy: I think a good way to think about it is that the 7nm node doesn't actually produce chips with 7nm features, it uses a "knife" (actually it's a lithography process) which is able to cut things as small as 7nm . That enables it to be more precise than a bigger "knife" so even though the size of the chip features is >7nm they are still able to be smaller than features cut with a 10nm "knife". I don't actually know anything about chip production. But that's what I've picked up from HN.
tmd83 6y ago
https://www.youtube.com/watch?v=3otqUu-7WUQ https://www.youtube.com/watch?v=3otqUu-7WUQ Surprising for the flashy marketing style of the video it really explained to me the difference between FINFET, GAA and MBCFET really well. Is Samsung and IBM stronger in structural R&D then they are at FABs?
- LargoLasskhyfv 6y ago
  Yes. That was a good one. Acessible.

110 points by Nokinside 6y ago

With this news, how much of a lead do they have over Intel now? When is Intel realistically going to ship their next node? Or is it all still perpetually delayed with no end in sight?

j4nt4b 6y ago

So is it safe to assume that Apple will book 100% of the first production runs for this new process as well?

vbezhenar 6y ago
I think it depends on price. At some point chips will cost too much for consumer electronics. You wouldn't want to buy iPhone with $1000 CPU.
- throwaway4good 6y ago
  A mass volume product like an iPhone is the only thing that generates enough money to sponsor this form of development.
  - marcosdumay 6y ago
    Yes, fabs take a large amount of risk when they develop new processes. That doesn't mean that Apple is interested. At least right now. Processes also tend to be improved with time.
- epicureanideal 6y ago
  Sign me up!
- mschuster91 6y ago
  > You wouldn't want to buy iPhone with $1000 CPU. 1.000 US$ no, but... I would not put it past Apple to make a literal system on chip. Like, one chip with everything on one die stack: CPU, GPU, RAM, cell modem, voltage regulators... the only external components would be ports and whatever cannot be reasonably expressed on a silicon die (e.g. coils for voltage regulators).
- AgloeDreams 6y ago
  Chips don't really work like that. 99% of the cost is in R&D and factory development then the cost per chip is pretty low, you just have to average in the R&D cost right? Apple sells ~ 200M units every year and prior developments get rolled into low cost products. Each new process probably leads Apple to make at least 500M devices. At scale you can spend 10s of billions on R&D and be spending less than $15-25 per chip.
- zamalek 6y ago
  Price depends on yields, and 90% is pretty damned good.
ksec 6y ago
It depends on a lot of factors, but mainly cost and yield. Example; Apple didn't use any 7nm EUV variant in A12/A13. While Huawei used it for their SoC. Having said that MBCFET, or more commonly known as GAA was originally scheduled for 3nm in 2022, so giving another 2 year to bake should help. So yes, if everything were executed to absolute perfection, then we should see a 2nm Apple Silicon in 2024. Note: While Wccftech has gotten a lot better in the recent 12 months or so, I still wouldn't put them into reliable and trusted source. It is good for rumours and entertainment, but that is about it. ( Personally I would rather not have it appear on HN )

throwaway4good 6y ago

Is TSMC the only who is close to doing this? What about Samsung or Intel? Or research labs that do smaller runs?

vbezhenar 6y ago
I think that Intel is one step behind. They'll likely produce 7nm in 2024 which should be comparable with TSMC 5nm. But TSMC 5nm already available for Apple.
- derision 6y ago
  Intel is more like 3 steps behind, one of their shoes is missing and the other is missing laces
  - hinkley 6y ago
    Having lived inside similar but much smaller dramas, it smells to me like Intel is titrating bad news. There was a goal. The goal became PR. Someone in management began to believe the PR, and turned it into a promise, predicated on 'and then a miracle occurs' (the engineers figure out how to do some things that haven't been done before). The engineers keep trying to explain how nobody has done this before because you can't. To do so involves violating the laws of physics or Information Theory. Anyone who cracks this problem deserves a Nobel nomination, so that probably isn't us. Middle management is stuck in the middle because someone has made promises we can't keep, and they either make it worse or help cover it up by playing for time. You either solve a different problem that has similar behavior (or at least, until researchers discover Meltdown), or you slowly reset expectations until people are chronically grumpy but nobody is yelling.
    - reducesuffering 6y ago
      This exact scenario is parodied in the show Silicon Valley[0] It's probably fairly commonplace. [0] https://www.youtube.com/watch?v=QZ7m7mV864A https://www.youtube.com/watch?v=QZ7m7mV864A

jmt_ 6y ago

Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?

vkou 6y ago
It's easy. You take a very small number, add the letters 'nm' to it, and then start sending out press-releases to the major media outlets. That number has nearly zero bearing on the actual physical sizes of the chip's components. The only people who know about the exact dimensions are the firms placing manufacturing contracts with TSMC.
- vmception 6y ago
  You get it
- gruez 6y ago
  >That number has nearly zero bearing on the actual physical sizes of the chip's components. AFAIK the reason behind this madness is that the number previously did correspond to feature size, but then they discovered methods of increasing transistor density without decreasing the size of the components. Since the feature size was used in marketing as a proxy for transistor density, they felt it was ultimately justified to decrease the number. After all, if your enhanced 32nm process provided the same transistor density as your competitor's 22nm process, why shouldn't you market your process as "22nm"?
  - egsmi 6y ago
    That number used to set the scale for the design rule set. https://www.electronics-tutorial.net/Digital-CMOS-Design/CMOS-Layout-Design/CMOS-lambda-Design-Rules/ https://www.electronics-tutorial.net/Digital-CMOS-Design/CMO...
nicoburns 6y ago
To make an analogy: I think a good way to think about it is that the 7nm node doesn't actually produce chips with 7nm features, it uses a "knife" (actually it's a lithography process) which is able to cut things as small as 7nm . That enables it to be more precise than a bigger "knife" so even though the size of the chip features is >7nm they are still able to be smaller than features cut with a 10nm "knife". I don't actually know anything about chip production. But that's what I've picked up from HN.

tmd83 6y ago

https://www.youtube.com/watch?v=3otqUu-7WUQ https://www.youtube.com/watch?v=3otqUu-7WUQ Surprising for the flashy marketing style of the video it really explained to me the difference between FINFET, GAA and MBCFET really well. Is Samsung and IBM stronger in structural R&D then they are at FABs?

LargoLasskhyfv 6y ago
Yes. That was a good one. Acessible.