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The writing's been on the wall for MIPS for ages. AFAIK it's not better than ARM in any meaningful way.
by api 7y ago
The writing's been on the wall for MIPS for ages. AFAIK it's not better than ARM in any meaningful way.
- unixhero 7y agoWell, good times were had!
- yjftsjthsd-h 7y agoLicensing?
- variaga 7y agoMy experience is that MIPS and ARM licensing are equally bad. As an anecdote, I have personally switched a MIPS core to an ARM core in an SoC revision specifically because ARM gave us better licensing terms than MIPS. It was a pain because MIPS big endian and ARM big endian are not directly compatible with each other.
- notacoward 7y agoMaybe it has changed, or maybe it depends on what level of IP you're licensing. The company I worked at in 2006-2009 had gone with MIPS because they were incorporating that with all sorts of other logic (from third parties plus custom) and the cost for that type of license from Arm would have bankrupted them instantly.
- boznz 7y agoIsnt mips open source ?
- pm321 7y agoThe creator of ARM speaks well of RISC-V and considers ARM yesterday's old news and has moved on. Comparing MIPS to ARM in essentials of architecture is MIPS more beautiful? ARM I understand is a mess that has evolved for its niche.
- arnd 7y agoI find the latest architecture versions are all remarkably similar as they have all adapted to the same environment: The old 32-bit Arm (now called Aarch32) was quite different and only somewhat RISC-like. Arm's Aarch64 however is mostly derived from MIPS64 with a lot of modernization plus some parts (exception levels) from 32-bit Arm. MIPSr6 was an attempt of modernizing MIPSr5 by removing all the ugly bits (delay slots!) but the incompatible instruction encoding prevented it from being widely adopted. You cannot buy a single MIPSr6 machine that a mainline Linux runs on. RISC-V's design looked at all RISC architectures (Berkely RISC, MIPS, SPARC, Power, Arm, ...) for inspiration and took the best parts of each. Leaving out all the historic baggage means it's simpler (the manual is a fraction of the size), but most of the important decisions are the same as in MIPSr6 and Armv8/Aarch64. One notable difference is the handling of compressed (16-bit) instructions: ARMv8/Aarch64 doesn't have them at all (like RISC-I/RISC-II, ARMv3 and MIPS-V), MIPSr6/microMIPS needs to switch between formats (like ARMv4T through ARMv6) and in RISC-V they are optional but can be freely mixed (somewhat like ARMv7 and nanoMIPS).
- ncmncm 7y agoIt's disappointing that RISC-V designers swallowed myths that resulted in unpleasant ISA details. For example, the notion that condition codes interfere with OoO execution has been repudiated; Power and x86 both now rename condition registers. Lack of popcount and rotate in the base instruction set are glaring omissions. (That x86 got popcount late, and that the bitmanip extension will have them if it ever gets ratified, are no excuse.) It was silly to make the compare instruction generate a 1 instead of the overwhelmingly more useful ~0. We only get a new ISA once in a generation. It is tragic when it is wrong. It is possible, in principle, that popcount and rotate could be added to the base 16-bit instructions, but I'm not holding my breath.