arnd

4 ms·

1.
by arnd 5y ago
No, it only means that Rockchips (or one of their customers) ships a kernel with a a driver for a Marvell wireless devices (presumably now made by NXP), for which Marvell claims to own the copyright and gives permission under GPL. Assuming
2.
by arnd 5y ago
M1 is Armv8.5-A, which is almost the same as Armv9.0-A, except that it lacks SVE2 vector instructions. Apple's CPUs tend to move to the latest architecture revision that is available at the time the instruction set gets nailed down, so
3.
by arnd 5y ago
Some of the Apple M1 changes went into the tty/serial driver tree that GregKH maintains. The actual platform code requires those changes, so we based the branch on top of that, and the top-level merge commit contains all of these. htt
4.
by arnd 6y ago
MIPSr6, aarch64 and riscv are siblings born from MIPSr5 plus the best of other RISC architectures. ppc64le and 32-bit Arm are part of the wider family, but have some notable differences that make them slightly less RISC-like. Both include e
5.
by arnd 6y ago
They are using risc-v for their 64-bit cores now.
6.
by arnd 6y ago
Mips R6 (Warrior m62xx/i6400/i6500/p6600) was already somewhat incompatible with R5 and earlier, the seventh generation nanomips i7200 was incompatible with that again.
7.
by arnd 6y ago
The next "loongarch" generation was already announced to move away from mips as the underlying ISA but instead allow running mips, arm64, risc-v, and x86 code in hardware assisted emulation.
8.
by arnd 6y ago
I double-checked the numbers reported by the driver against doing actual writes to the file system and the numbers reported by the OS, and they match exactly when there is no other activity: writing a 1GB file increases the number by 1GB an
9.
by arnd 6y ago
It was apparently built for a very specific use case (doing CI for some application) so I guess it has to be ARM Linux. You can run Linux in a VM guest on Mac mini, but some limitations remain: - The project was obviously started before the
10.
by arnd 6y ago
User space doesn't generally deal well with time going backwards, but the main problem is that setting an absolute timeout in a program is broken when the target time is less than the current time. An example of this is 32-bit systemd,
11.
by arnd 6y ago
I think you get into practical problems at some point. WikiChip lists a 28nm Cortex-A7 core at 0.48mm², with every node shrink (20nm, 14nm, 10nm, 7nm, ...) you can halve that, but adding 64-bit support to a core might only add about 10%. Yo
12.
by arnd 6y ago
That sweet spot for cost has already moved from 40nm to 28nm for most of the market. The new SAM9X60 I mentioned is still on 40nm, but it's a tiny chip and all new Cortex-A7 SoCs and things like the Ingenic X2000 are on 28nm because of
13.
by arnd 6y ago
I tried not to talk too much about 64-bit architectures, but that's a good point. Indeed not just Alpha but also MIPS R4000, UltraSPARC, PA-8000 were already around in the 1990s when the 32-bit kernel support got merged, while ppc64, s
14.
by arnd 6y ago
musl has completed the move with version 1.2, and embedded distros are moving to that. glibc time64 support is still work in progress, as I wrote in the article
15.
by arnd 6y ago
32-bit Arm has some features that make it less RISC-like than others: - Predication as a major architectural feature -- every instruction can be conditionally executed - Complex load-store instructions: ldm/stm can operate on a large s
16.
by arnd 6y ago
I find the latest architecture versions are all remarkably similar as they have all adapted to the same environment: The old 32-bit Arm (now called Aarch32) was quite different and only somewhat RISC-like. Arm's Aarch64 however is most
17.
by arnd 6y ago
Ingenic an Loongson both have architecture licenses and so far have kept releasing new chips with their own cores on a regular basis, including (in Loongson's case) some interesting enhancements. Both are also members in the RISC-V fou