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ZipCPU – A small, lightweight, RISC soft core in Verilog
- eterps 7y agoI always wonder why Niklaus Wirth's RISC5 architecture[1] (not to be confused with RISC-V) doesn't get more love. From my perspective (but I'm no expert on this) it seems exceptionally simple and elegant while still being able to run a desktop OS [2]. [1] https://inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC.pdf https://inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC.pdf [2] https://i.redd.it/ukagn6imtiv01.png https://i.redd.it/ukagn6imtiv01.png
- tyingq 7y agoProbably doesn't help that googling for "risc5" brings back RISC-V results.
- eterps 7y agoMore links: https://pdfs.semanticscholar.org/2c11/7c1456eb96bbea19aa3c8b018de4fc9387bc.pdf https://pdfs.semanticscholar.org/2c11/7c1456eb96bbea19aa3c8b... http://www.projectoberon.com/ http://www.projectoberon.com/ https://www.reddit.com/r/unixporn/comments/8gllm9/oberon_oberon/ https://www.reddit.com/r/unixporn/comments/8gllm9/oberon_obe...
- rwmj 7y agoOf course developers are free to do what they like, but I think it's a bit of a shame that it's not RISC-V. He's missing out on all the toolchain support in GCC and Clang, plus the ability to run various embedded operating systems including these days seL4. RISC-V has an embedded profile (RV32E) and a tiny implementation of that (PicoRV32) so I'm fairly sure it could be suitable for this.
- tyingq 7y agoHe points out the reasons it is the way it is here: http://zipcpu.com/about/zipcpu.html http://zipcpu.com/about/zipcpu.html
- debatem1 7y agoI don't see anything specific about riscv here, am I missing something?
- tyingq 7y agoReasons like learning, very small #LUT devices, etc, that wouldn't be satisfied with 32 bit Linux capable RISCV. For example "I wanted to know how to build a CPU. This includes learning how to build not only a CPU, but also backends for the C-library, GCC and binutils (GDB soon to come)."
- jdsully 7y agoZipCPU predates the Risc-V buzz and is more a lightweight alternative to things like the microblaze. Its for when you want a microcontroller on your FPGA.
- bem94 7y agoAs others have said, this pre-dates RISC-V. The author built it as a teaching / learning aid and blogs about it excellently: https://zipcpu.com/ https://zipcpu.com/ More generally, anyone building their own CPU and architecture just for kicks gets serious kudos in my book. It's not a shame, it's brilliant!
- 7y ago
- jacobush 7y agoGPLv3 may cause issues when embedding it in your own SoC or whatever, especially given the very proprietary nature of toolchains. Not that I mind, just sayin'
- jsjohnst 7y ago> Because Gisselquist Technology, LLC, owns all of the code for the ZipCPU and its peripherals, proprietary licenses may be purchased.
- lnsru 7y agoIt’s open source, but not free. MicroBlaze MCS is free, but not open source: https://www.xilinx.com/products/design-tools/mb-mcs.html https://www.xilinx.com/products/design-tools/mb-mcs.html Thank you very much for this comment about proprietary license!
- jhauris 7y agoI don't understand why you're saying it isn't free. Are you saying that because it's dual licensed it's not free? Users would still be able to modify and fork the GPL version in all the normal ways.
- lnsru 7y agoIf I want to use it in my closed source project I must pay to Gisselquist Technology, LLC. Or I am wrong here?
- zipcpu 7y agoIf you want to use it in your closed source project, give me a holler. I'm sure we could work something out. Even if we don't, I'd love to have the opportunity to hear from you, meet you, say hello, and encourage you in any way I can.
- TomVDB 7y ago
- bjt2n3904 7y agoThis guy posts some amazing content on Twitter, his account is really fun to follow.
- zackmorris 7y agoFound some info in the repo's issues about how much room ZipCPU takes on an FPGA: https://github.com/ZipCPU/zipcpu/issues/8 https://github.com/ZipCPU/zipcpu/issues/8 PDFs: https://github.com/ZipCPU/zipcpu/blob/master/doc/orconf.pdf https://github.com/ZipCPU/zipcpu/blob/master/doc/orconf.pdf https://github.com/ZipCPU/zipcpu/blob/master/doc/orconf2017.pdf https://github.com/ZipCPU/zipcpu/blob/master/doc/orconf2017.... https://github.com/ZipCPU/zipcpu/blob/master/doc/orconf2018.pdf https://github.com/ZipCPU/zipcpu/blob/master/doc/orconf2018.... Also a list of FPGA dev boards as of 2018: https://www.reddit.com/r/FPGA/comments/9yutk8/best_100300_fpga_development_board_in_2018/ https://www.reddit.com/r/FPGA/comments/9yutk8/best_100300_fp... So looks like ZipCPU takes between 2400 and 7372 LUTs, depending on how optimized the routing is. An Ultra96 with 154k LUTs could hold between about 20 and 64 ZipCPUs, although busses would be an issue. I'd like to see more of these projects start from a stance of connecting to other CPUs on the same chip rather than out to main memory. Or rather, a spec should only be considered complete when it has designs for both an in-mesh core to be placed beside its neighbors in a grid, and a bus-facing core for connecting out to main memory. I think the future is going to be a series of basic blocks like CPUs, RAMs, maybe even GPUs that can be placed arbitrarily and run as clusters for tackling big data problems using techniques like map reduce. Or better yet, maybe FPGAs that look like multiple FPGAs (each with their own RAM) running on the same chip.
- sehugg 7y agoBing has been using soft-core processors for search, 240 threads per FPGA: https://www.enterpriseai.news/2014/09/03/microsoft-using-fpgas-speed-bing-search/ https://www.enterpriseai.news/2014/09/03/microsoft-using-fpg...
- kitd 7y agoNoob question: would what you describe be equivalent to what transputers were intended for?
- zipcpu 7y agoI have yet to place more than two ZipCPU's on a board, mostly because I'm still working out the various bus details associated with making multiple CPUs the master of the same bus. For example, should they all have the same perspective of the address map? This I'm still working out.
- sehugg 7y agoI didn't know yosys did formal verification now: http://zipcpu.com/blog/2017/10/19/formal-intro.html http://zipcpu.com/blog/2017/10/19/formal-intro.html Cool.
- zipcpu 7y agoIf that article interests you, you might find this one even more interesting: http://zipcpu.com/blog/2018/04/02/formal-cpu-bugs.html http://zipcpu.com/blog/2018/04/02/formal-cpu-bugs.html Basically, I was shocked when I applied SymbiYosys to the ZipCPU at how many bugs I found. Bug lists like this are typically company secrets, since no one wants to reveal how many bugs their product has. In my case, part of my success has been my openness.
- bayesian_horse 7y agoJust out of curiosity: What exactly would you need this for? Is it just about learning how to design a CPU? Is it about solving a specific task a soft core on an FPGA can do better? What kind of use cases are there where an FPGA with a RISC core is better suited than some kind of microprocessor?
- q3k 7y agoSometimes when designing for an FPGA/ASIC, the easiest way to implement some sort of complex control logic is to use a small CPU. For example, the Nvidia Tegra X1 SoC contains a handful of Falcon CPUs (proprietary ISA and core), responsible for amongst others: - USB 3.0 command/event processing - Video Image Compositor 'inverse telecine' processing - HDMI security Same goes for your nVidia PC GPUs - they have Falcons sprinkled across the entire thing.
- rcxdude 7y agoHeck, one SoC I know of has an entire cortex M3 core to manage entering and exiting sleep modes.
- zipcpu 7y agoThink of it this way, what do you need an FPGA for? Now, when budgets are tight, how do you pack more bang for your buck? Rather than placing more and more state machines on an FPGA, you can offload such task loads onto a CPU. Indeed, the more (slow, not time-sensitive, complex, etc) tasks you can off load onto the CPU, the more fabric is available for ... whatever task you actually wanted to place onto the FPGA.
- bayesian_horse 7y agoHm, but then why don't they use a discrete CPU built for this purpose? Many FPGA development boards already come with an ARM MCU. I'd guess that when the CPU core is on the FPGA, the communication between the CPU and whatever the custom logic does is faster and more in-sync. Thank you for answering. I have seen a couple of resources on using FPGAs, with those being increasingly accessible to "hobbyists". I often fail to see the "why" in the examples.
- GeorgeTirebiter 7y agoJan Gray is, I think, more-or-less the Godfather of this approach. I especially enjoyed his Circuit Cellar 3-part series where he describes and builds the xr16 -- a 16-bit machine whose instruction set is designed to well-match the LUT capabilities of an FPGA. I implemented it, and with the LCC C compiler, I was able to run plenty of code. Start here: https://github.com/BigEd/XSOC-xr16/blob/master/doc/xsoc-talk.pdf https://github.com/BigEd/XSOC-xr16/blob/master/doc/xsoc-talk... which is the presentation; then check out the rest of the repo doc: https://github.com/BigEd/XSOC-xr16/tree/master/doc https://github.com/BigEd/XSOC-xr16/tree/master/doc and although it's not maintained these days, his old site is also useful: http://www.fpgacpu.org/xsoc/xr16.html http://www.fpgacpu.org/xsoc/xr16.html for more modern stuff, see http://fpga.org/ http://fpga.org/
- zipcpu 7y agoJan Gray is one of my heroes. I definitely look up to him, and I've enjoyed my interactions with him and the encouragement and advice he's offered me.
- dang 7y agoA thread from 10 months ago: https://news.ycombinator.com/item?id=18138174 https://news.ycombinator.com/item?id=18138174 Half a dozen blog post discussions as well: https://hn.algolia.com/?query=ZipCPU%20points%3E10&sort=byDate&dateRange=all&type=story&storyText=false&prefix=false&page=0 https://hn.algolia.com/?query=ZipCPU%20points%3E10&sort=byDa...