zipcpu

4 ms·

1.
by zipcpu 7y ago
I'm not sure I followed all of that, but let me at least try to look up the links and see what I can learn. Maybe they'll help me follow the concepts you are suggesting. Dan
2.
by zipcpu 7y ago
If you want to use it in your closed source project, give me a holler. I'm sure we could work something out. Even if we don't, I'd love to have the opportunity to hear from you, meet you, say hello, and encourage you in any
3.
by zipcpu 7y ago
Realistically, those who've wanted to use the ZipCPU tend to just chat with me about it and we work out a handshake agreement or some such. Were someone to want to use it in a commercial product, I'd be more interested in some for
4.
by zipcpu 7y ago
If that article interests you, you might find this one even more interesting: http://zipcpu.com/blog/2018/04/02/formal-cpu-bugs.html Basically, I was shocked when I applied SymbiYosys to the ZipCPU at ho
5.
by zipcpu 7y ago
Next week's project will be programming the software for a PicoRV inside the bus structure created by AutoFPGA, so I am very aware of the RISC-V architectures ... now. I would very much like to build a RISC-V 64-bit variant (there are
6.
by zipcpu 7y ago
Think of it this way, what do you need an FPGA for? Now, when budgets are tight, how do you pack more bang for your buck? Rather than placing more and more state machines on an FPGA, you can offload such task loads onto a CPU. Indeed, th
7.
by zipcpu 7y ago
I have yet to place more than two ZipCPU's on a board, mostly because I'm still working out the various bus details associated with making multiple CPUs the master of the same bus. For example, should they all have the same persp
8.
by zipcpu 7y ago
Jan Gray is one of my heroes. I definitely look up to him, and I've enjoyed my interactions with him and the encouragement and advice he's offered me.
9.
by zipcpu 8y ago
Check out page ix in the preface.
10.
by zipcpu 8y ago
You could even do it if you wanted an ASIC. FPGA's are commonly used for verifying the logic that will eventually get placed into an ASIC.
11.
by zipcpu 8y ago
All of the ZipCPU's cache implementations have been formally verified using SymbiYosys--an open source, free-as-beer product.
12.
by zipcpu 8y ago
The ZipCPU and several peripherals can fit within an iCE40 8k using only about 5k LUTs--and that's with the multiply unit, the divide unit, the pipelined fetch unit, and a debugging bus infrastructure. While that isn't the full p
13.
by zipcpu 8y ago
I actually started the project almost a year earlier, and made many mistakes before finally presenting at ORCONF in September of 2016. That said, I am considering a RISC-V compatible design. I just haven't committed to doing so.
14.
by zipcpu 8y ago
The specification actually mentions RISC-V, and why I didn't use it. In hind sight, it's harder to decode the RISC-V instruction set than the one for the ZipCPU--to many holes in strange places.
15.
by zipcpu 8y ago
Yes, the GPLv3 license is applied to both the core generator and the generated code. Copyleft is quite appropriate for simulations: they are all software, and the user is not likely to "convey" that software to another. Even if h
16.
by zipcpu 8y ago
@matt_d: Thanks for the cross-post!
17.
by zipcpu 9y ago
Freenode has several FPGA related channels. Among them are ##fpga, ##verilog, and ##vhdl.
18.
by zipcpu 9y ago
Thanks for the complement! I'm actually the only one who has posted on the site.
19.
by zipcpu 9y ago
As the author of the article ... I was also self-taught. Dan
20.
by zipcpu 9y ago
Thank you for that comment. I've adjusted the text so that it's hopefully clearer! Dan