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I'm sorry, did you just describe the core advantage of a new RISC CPU against incumbents as smaller code size? Where am I, and what is happening?
by ip26 8y ago
I'm sorry, did you just describe the core advantage of a new RISC CPU against incumbents as smaller code size? Where am I, and what is happening?
- hrydgard 8y agoStill matters in many embedded applications.
- 0x1DEACAFE 8y agoCode size for RV32IMAC is still pretty mediocre with the current GCC/RISCV compiler. And the standard library they use by default is pretty sub-optimal. I know they're working on it, and it's clear they're making quick progress, but it's not easy at the moment. The last project I worked on, I had to abandon ABI conventions and hand craft large chunks of code.
- zerohp 8y agoSmaller code size makes your caches more effective. L1 instruction cache is size limited because it's on a critical timing path. Increasing its size limits your operating frequency.
- dbcurtis 8y agoIs it a core advantage? Maybe. But smaller code size has beneficial effects on the silicon cost. Choice 1: If you can benchmark the same on important work loads with 10% smaller I-Cache, make the die smaller. Manufacturing costs go down with a greater than square law effect with die area. Choice 2: Use the die area freed up to put more functional units in the same area. Core advantage? I will let others debate that. Significant: surely.
- imtringued 8y agoThat's a pretty damn good argument. It's 10% ahead of the best ISAs that took decades of development. Just think of how adoption would be affected if it was 30% worse. In other words: not only is it better in terms of royalties and ecosystem, it also better at everything else too. Isn't that terrific?
- marcosdumay 8y agoI read the GP as talking about how code size was always a weakness of RISC, and seemingly the largest one. And here it is compared against a classical CISC platform and a hybrid one highly optimized for code size, and winning. What just makes RISC-V even more awesome than just any non-optimized design beating the incumbents.
- deleted 8y ago[deleted]
- wmf 8y agoRISC-V has a code compression extension so it's not classic RISC but it's still far simpler than CISC. https://riscv.org/wp-content/uploads/2015/05/riscv-compressed-spec-v1.7.pdf https://riscv.org/wp-content/uploads/2015/05/riscv-compresse...
- pcwalton 8y agox86-64 isn't very space efficient anymore, so it's not hard to beat. Even AArch64, with a fixed 32-bit instruction size, competes well with x86-64. REX prefixes really killed the space efficiency of the x86 architecture.