9 ms·

Verilog sources for Western Digital's open source RISC-V core

320 points by obl 8y ago

m0zg 8y ago
First of all, kudos to WD. This makes me feel good about spending $1500 on their spinning drives just last week. But on a more practical note, what kind of board and toolchain does one need to get this going on an FPGA? Is there a readme somewhere that would walk one through the process?
- _chris_ 8y ago
  The core speaks AXI and AHB-Lite, so for an experienced FPGA/core guy, it probably wouldn't be too much work to integrate into their own FPGA flow. And since it doesn't have any floating-point, it will probably be able to fit on modestly-sized FPGAs.
- FPGAhacker 8y ago
  Depends on what you want to do I guess. You'd need a SoC variety of FPGA with a memory controller as I didn't see one in this code base. Putting this in an FPGA seems feasible. But I see some challenges. It looks like it's a Harvard-architecture core. That means separate buses for data and instructions, which is not common outside of embedded or specialized systems. I'm sure you can setup GCC to work with this, but it would be a project. You could build (or find) a memory controller that can multiplex separate instruction and data buses to a single memory space... decide data will be in memory range A and instructions in memory range B, and inform the linker where to put code and data. I'd probably start by downloading whatever free versions of the fpga tools the vender's offer and see if I can synthesize the code with any of the targets and how well it fit. (assuming someone else hasn't posted that info already). If it isn't going to fit in anything supported by the free version of tools, I probably wouldn't go any further with it myself. Assuming that it did fit, I would switch gears and would build a simulation testbench, and start tinkering to see how it worked as compared to the docs. If it really is strictly harvard, I'd build a bridge to the FPGA's memory controller that could map two buses to a single memory space. If I got that far I'd start working setting up a compiler and linker to map out code and data partitions to that memory space. At this point you might be ready to build all this and load the FPGA, but you have no peripherals (like ethernet or a vga). I'd consider slaving it to a raspberry pi or something like that. I saw a debug module in the github repo, so that might be a good thing to expose to the raspberry pi. Or pick a simple bus like i2c and use that to get some visibility from the r-pi into the risc-v state and bridge over to the ram. --- Another direction you could take would be to get something like a snickerdoodle. I believe it can boot linux with the arm core in the FPGA, and it has the peripherals you need like ethernet(wifi) and access to an SD card. So the direction I would take there is trying to supplant the ARM core with the RISC-V. So the effort there would be to disable the ARM core, which ought to be straight forward, and build a wrapper around the RISC-V core to be able to talk to the peripherals in place of the ARM. Given that it's an ARM core, I'm sure all the internal busing is AMBA (AHB/APB/AXI), so it's probably pretty reasonable to try this.
  - m0zg 8y ago
    That sounds like considerably more work than I was hoping it would be. So the follow-up question, then. Who is this release for, in your opinion?
    - FPGAhacker 8y ago
      I don't know why WD released this, but it would be useful for people building SoC ASICs that don't want to license an ARM core. Depending on the licensing.
    - antpls 8y ago
      Maybe this will be picked as teaching material in universities by students or teachers, which means potential future candidates for WD. Maybe it's a way to help existing experts to federate around real use cases to discuss further field improvements, which means outsourced R&D for WD. Eventually, it will be less work in the future once more people get interested in the subject.
  - dbcurtis 8y ago
    > I'm sure you can setup GCC to work with this, but it would be a project. FWIW AVR is not only Harvard, but code memory addresses point to 16-bit words, and data pointers to bytes. Yet, gcc works great (mostly). It is mainly a matter of whipping up a good linker script and directing code and data to the appropriate sections. Not particularly hard, although Harvardness does leak into your C code, mostly when taking pointers to functions or literal sections stored in flash. *mostly — gcc long ago stopped taking optimization for code size seriously. Unfortunate for uCtlr users, as for small processors like the AVR optimization for size is pretty much also optimization for speed. Gcc has had some pretty serious code-size regressions in the past — but mostly not noticed by people not trying to shoehorn code into a tiny flash space.
    - haberman 8y ago
      It's surprising to me that the RISC-V ISA specification is loose enough that a core could be considered RISC-V-compliant and yet also need a linker script to accommodate its peculiarities.
- jhallenworld 8y ago
  I'm curious if the FPGA tools support the system verilog syntax that this is using. I'm an FPGA designer, but have not switched to system verilog.
eternal_virgin 8y ago
I've been meaning to get started with RISC-V for some time now but can't find much on it for total beginners online. Can anyone recommend a starting point for a total noob?
- eBombzor 8y ago
  Since RISC-V uses Chisel instead of Verilog, you will probably need this first: https://github.com/freechipsproject/chisel-bootcamp https://github.com/freechipsproject/chisel-bootcamp For actually learning RISC-V, you can check out these books: https://riscv.org/risc-v-books/ https://riscv.org/risc-v-books/ The Patterson and Hennessy book is a great starting point and the RISC-V reader is great reference.
  - dooglius 8y ago
    > Since RISC-V uses Chisel instead of Verilog What do you mean? The core here is entirely Verilog/SystemVerilog
    - mepian 8y ago
      I presume the parent generalized their experience with the BOOM and Rocket implementations of RISC-V, which do use Chisel, to the entire architecture.
    - eBombzor 8y ago
      Sorry I am an idiot how do I edit/delete my comment so I can erase this misinformation?
      - yjftsjthsd-h 8y ago
        Unfortunately, if you don't see an edit button on the comment then you can't edit it anymore. But props for admitting you're wrong and trying to correct it :-)
  - chrisseaton 8y ago
    > Since RISC-V uses Chisel instead of Verilog How can an ISA ‘use Chisel’? It’s a spec not an implementation.
dooglius 8y ago
They have an open-source software simulator for this as well: https://github.com/westerndigitalcorporation/swerv-ISS https://github.com/westerndigitalcorporation/swerv-ISS I'm curious how the performance compares to other open-source cores
- thesz 8y ago
  From cursory glance they have operand read bypass and branch prediction. Operand read bypass speeds things up considerably (factor is 1/N, where N is pipeline length) and the presence of branch prediction hints at speculative execution. There are two ALUs. It seems like highly performant core.
  - bogomipz 8y ago
    >"From cursory glance they have operand read bypass and branch prediction." I'm not familiar with "operand read bypass", is this the same thing as "operand forwarding"? Is this a pipeline optimization? Might you have any link you could share on this?
    - thesz 8y ago
      It is the same thing. Just different name.
ngcc_hk 8y ago
The link assume you know and this as well. May be in both has a few short paragraph for those not in to appreciate and say thx you.
equalunique 8y ago
Shut up and take my money!
sitkack 8y ago
Wester Digital if you are reading this! Pleeeeze I want to have access as an end user. I'd like to do a predicate push down and be able to write into the DRAM buffer and the flush a commit. Or pin certain blocks directly into DRAM. Pleeeeze!
- tyingq 8y ago
  This person got pretty far with the Marvell ARM WD drive controller in 2015: https://www.malwaretech.com/2015/04/hard-disk-firmware-hacking-part-1.html https://www.malwaretech.com/2015/04/hard-disk-firmware-hacki... Also see: http://spritesmods.com/?art=hddhack&page=1 http://spritesmods.com/?art=hddhack&page=1
- pkaye 8y ago
  What would you use this for?
quinta1k 8y ago
It would be their dream come true if the hw oss community (very small) takes this up and develops it into something huge like for sw projects. There is so much manpower needed to develop these kinds of things - what better way than oss. However, too little, too late, ee industry. An entire generation of top tier college students have pretty much skipped ee.
- jacoblambda 8y ago
  Nowadays the Computer Engineering degree lets those of us who were torn between EE and CS get both. At least at Virginia Tech, CpE(Computer Engineering) easily outstrips CS and teaches the basics of CS and EE fundamentals as well as practical application of both of them.
  - beatgammit 8y ago
    Sure, that makes sense in theory, but of the computer engineers I've known, they prefer one end or the other and aren't as good at either as someone dedicated to just one. However, this is a pretty small sample size (I helped interview at a small company), so I'm not sure if it's a trend.
    - jacoblambda 8y ago
      Ya most of us tend to prefer one side or the other but this system tends to be a good way to get create would be EEs with a decent bit of exposure to CS and vice versa. It doesn't create perfect mixed skills but give a working experience with both sides. For example I hate semiconductor work, dislike circuit analysis, and much prefer software but I enjoy working with VHDLs and embedded software. I'll take Rust or Haskell over Verilog any day but I have no problem working with VHDLs given the need.
      - deleted 8y ago
        [deleted]
- gumby 8y ago
gmueckl 8y ago
So this is the logic of the controller in Verilog. But I don't see any test scripts. I am not an expert in logic design, but it seems to me that validation is at least as expensive and time consuming as the actual creation because you cannot afford mistakes in the ASIC masks. Am I missing something here?
- noobiemcfoob 8y ago
  https://github.com/westerndigitalcorporation/swerv-ISS https://github.com/westerndigitalcorporation/swerv-ISS
  - KSteffensen 8y ago
    From a quick look this is a reference model, not a testbench. There is a lot of work needed, writing testbench environment, test cases, analyzing and writing coverage models etc. before the Verilog code can be considered verified and ready for ASIC tape-out. From my experience writing the design RTL code is at most 25% of the man hours. The rest is verification and some synthesis backend work.
- sweden 8y ago
  You are correct. The most difficult part of a design is not the design itself, it's all the documentation and the verification environment around it. This is a nice gesture but hardware is a bit different than software and dumping a bunch of RTL code is not really useful.
  - noobiemcfoob 8y ago
    A full environment that could get you to a blinking LED off of an FPGA would be the complete dump, but I don't see the value in downplaying publishing a bulk of code that all others have hidden behind lock and key.
ksec 8y ago
How does it compare to BOOM [1], both RISC-V and both open source. [1] https://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom Edit: Not sure why I am getting downvoted, isn't this a valid question?
- tyingq 8y ago
  This one doesn't have out of order processing, a FPU, or a MMU. It's also 32 bit where BOOM is 64. Edit: There is a little more detail available for an existing Marvell ARM SATA controller (similar to what WD uses now), which this processor is probably the replacement for[1]. That indicates it has 2 ARM Cortex R4 cores. On the Cortex R4, it looks like the FPU is an optional feature, and there is no MMU, just an MPU[2]. Basically, it looks like the BOOM CPU is intended to be a general purpose CPU, and this is intended to be a very fast/capable microcontroller. It wouldn't run Linux, other than maybe something like uClinux. It does look to be potentially REALLY fast. See https://www.anandtech.com/show/13678/western-digital-reveals-swerv-risc-v-core-and-omnixtend-coherency-tech https://www.anandtech.com/show/13678/western-digital-reveals... [1] https://www.marvell.com/storage/assets/Marvell_88i9441_Soleil-H_pb_FINAL.pdf https://www.marvell.com/storage/assets/Marvell_88i9441_Solei... [2] https://developer.arm.com/products/processors/cortex-r/cortex-r4 https://developer.arm.com/products/processors/cortex-r/corte...
- garmaine 8y ago
  Because you’re comparing a workstation class out-of-order CPU design to a teeny tiny embedded chip lacking an FPU or even a unified code/data cache. It’s like saying “how does the Intel Atom compare against the AMD Ryzen Threadripper core?”
  - TomVDB 8y ago
    Compared to the most other RV32 soft core implementations, this one is far from being teeny tiny!
zapdrive 8y ago
Is this code just for a processor, or an SOC? How is this different from the open source Shakti processor being designed by IIT Chennai?
xvilka 8y ago
Would have been awesome if they joined the effort of developing FIRRTL[1][2] and using it as a universal (LLVM-alike) hardware intermediate language, better suited modern chip design needs than Verilog or VHDL[3]. [1] https://github.com/freechipsproject/FIRRTL https://github.com/freechipsproject/FIRRTL [2] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/11/Reusability-is-FIRRTL-Ground-Izraelevitz.pdf https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/... [3] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19
- diarmuidc 8y ago
  A HDL that no one in the industry uses?
- NotCamelCase 8y ago
  It's a neat idea, but to me, that's like it. For SW, LLVM serves two-way: 1)target any (supported) arch you like with your language of choice, 2)customize your toolchain to generate native machine code (i.e. GPU shader langauges) from any (supported) language. I'd say putting yet another middleman between your logic compiler/netlist and what you actually use is not the best course of action for HW implementations. Even HLS has a big friction for use and is hardly picked up, with its obvious, immediate advantages.
glenrivard 8y ago
I am a bit older and seen a lot of tech come and go. RISC-V is something that feels like it is going to be really, really big. It has so much momentum so quickly.
nraynaud 8y ago
Can someone explain a bit what’s happening around the division? https://github.com/westerndigitalcorporation/swerv_eh1/blob/master/design/exu/exu_div_ctl.sv https://github.com/westerndigitalcorporation/swerv_eh1/blob/... Or give me some google keywords? Is there a link with the pentium bug?
- yjftsjthsd-h 8y ago
  This? https://en.m.wikipedia.org/wiki/Pentium_FDIV_bug https://en.m.wikipedia.org/wiki/Pentium_FDIV_bug Edit: This is just the top result from https://duckduckgo.com/?q=pentium+cpu+bug https://duckduckgo.com/?q=pentium+cpu+bug
  - nraynaud 8y ago
    Link-> relationship
- jhallenworld 8y ago
  I like the small number case: they use a very old logic minimization program to generate the equations for it: https://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer https://en.wikipedia.org/wiki/Espresso_heuristic_logic_minim... Otherwise it's taking 32 cycles to do the division. There is a count for this.
Rochus 8y ago
Great work, many thanks to WD. As far as I see only a subset of the SystemVerilog features is used. Is there a "coding standard" somewhere available specifying this subset with a rationale? Is it mostly to be compatible with Verilator? Is there information available why they used Verilator and how it has proven itself?

320 points by obl 8y ago

m0zg 8y ago

First of all, kudos to WD. This makes me feel good about spending $1500 on their spinning drives just last week. But on a more practical note, what kind of board and toolchain does one need to get this going on an FPGA? Is there a readme somewhere that would walk one through the process?

_chris_ 8y ago
The core speaks AXI and AHB-Lite, so for an experienced FPGA/core guy, it probably wouldn't be too much work to integrate into their own FPGA flow. And since it doesn't have any floating-point, it will probably be able to fit on modestly-sized FPGAs.
FPGAhacker 8y ago
Depends on what you want to do I guess. You'd need a SoC variety of FPGA with a memory controller as I didn't see one in this code base. Putting this in an FPGA seems feasible. But I see some challenges. It looks like it's a Harvard-architecture core. That means separate buses for data and instructions, which is not common outside of embedded or specialized systems. I'm sure you can setup GCC to work with this, but it would be a project. You could build (or find) a memory controller that can multiplex separate instruction and data buses to a single memory space... decide data will be in memory range A and instructions in memory range B, and inform the linker where to put code and data. I'd probably start by downloading whatever free versions of the fpga tools the vender's offer and see if I can synthesize the code with any of the targets and how well it fit. (assuming someone else hasn't posted that info already). If it isn't going to fit in anything supported by the free version of tools, I probably wouldn't go any further with it myself. Assuming that it did fit, I would switch gears and would build a simulation testbench, and start tinkering to see how it worked as compared to the docs. If it really is strictly harvard, I'd build a bridge to the FPGA's memory controller that could map two buses to a single memory space. If I got that far I'd start working setting up a compiler and linker to map out code and data partitions to that memory space. At this point you might be ready to build all this and load the FPGA, but you have no peripherals (like ethernet or a vga). I'd consider slaving it to a raspberry pi or something like that. I saw a debug module in the github repo, so that might be a good thing to expose to the raspberry pi. Or pick a simple bus like i2c and use that to get some visibility from the r-pi into the risc-v state and bridge over to the ram. --- Another direction you could take would be to get something like a snickerdoodle. I believe it can boot linux with the arm core in the FPGA, and it has the peripherals you need like ethernet(wifi) and access to an SD card. So the direction I would take there is trying to supplant the ARM core with the RISC-V. So the effort there would be to disable the ARM core, which ought to be straight forward, and build a wrapper around the RISC-V core to be able to talk to the peripherals in place of the ARM. Given that it's an ARM core, I'm sure all the internal busing is AMBA (AHB/APB/AXI), so it's probably pretty reasonable to try this.
- m0zg 8y ago
  That sounds like considerably more work than I was hoping it would be. So the follow-up question, then. Who is this release for, in your opinion?
  - FPGAhacker 8y ago
    I don't know why WD released this, but it would be useful for people building SoC ASICs that don't want to license an ARM core. Depending on the licensing.
  - antpls 8y ago
    Maybe this will be picked as teaching material in universities by students or teachers, which means potential future candidates for WD. Maybe it's a way to help existing experts to federate around real use cases to discuss further field improvements, which means outsourced R&D for WD. Eventually, it will be less work in the future once more people get interested in the subject.
- dbcurtis 8y ago
  > I'm sure you can setup GCC to work with this, but it would be a project. FWIW AVR is not only Harvard, but code memory addresses point to 16-bit words, and data pointers to bytes. Yet, gcc works great (mostly). It is mainly a matter of whipping up a good linker script and directing code and data to the appropriate sections. Not particularly hard, although Harvardness does leak into your C code, mostly when taking pointers to functions or literal sections stored in flash. *mostly — gcc long ago stopped taking optimization for code size seriously. Unfortunate for uCtlr users, as for small processors like the AVR optimization for size is pretty much also optimization for speed. Gcc has had some pretty serious code-size regressions in the past — but mostly not noticed by people not trying to shoehorn code into a tiny flash space.
  - haberman 8y ago
    It's surprising to me that the RISC-V ISA specification is loose enough that a core could be considered RISC-V-compliant and yet also need a linker script to accommodate its peculiarities.
jhallenworld 8y ago
I'm curious if the FPGA tools support the system verilog syntax that this is using. I'm an FPGA designer, but have not switched to system verilog.

eternal_virgin 8y ago

I've been meaning to get started with RISC-V for some time now but can't find much on it for total beginners online. Can anyone recommend a starting point for a total noob?

eBombzor 8y ago
Since RISC-V uses Chisel instead of Verilog, you will probably need this first: https://github.com/freechipsproject/chisel-bootcamp https://github.com/freechipsproject/chisel-bootcamp For actually learning RISC-V, you can check out these books: https://riscv.org/risc-v-books/ https://riscv.org/risc-v-books/ The Patterson and Hennessy book is a great starting point and the RISC-V reader is great reference.
- dooglius 8y ago
  > Since RISC-V uses Chisel instead of Verilog What do you mean? The core here is entirely Verilog/SystemVerilog
  - mepian 8y ago
    I presume the parent generalized their experience with the BOOM and Rocket implementations of RISC-V, which do use Chisel, to the entire architecture.
  - eBombzor 8y ago
    Sorry I am an idiot how do I edit/delete my comment so I can erase this misinformation?
    - yjftsjthsd-h 8y ago
      Unfortunately, if you don't see an edit button on the comment then you can't edit it anymore. But props for admitting you're wrong and trying to correct it :-)
- chrisseaton 8y ago
  > Since RISC-V uses Chisel instead of Verilog How can an ISA ‘use Chisel’? It’s a spec not an implementation.

dooglius 8y ago

They have an open-source software simulator for this as well: https://github.com/westerndigitalcorporation/swerv-ISS https://github.com/westerndigitalcorporation/swerv-ISS I'm curious how the performance compares to other open-source cores

thesz 8y ago
From cursory glance they have operand read bypass and branch prediction. Operand read bypass speeds things up considerably (factor is 1/N, where N is pipeline length) and the presence of branch prediction hints at speculative execution. There are two ALUs. It seems like highly performant core.
- bogomipz 8y ago
  >"From cursory glance they have operand read bypass and branch prediction." I'm not familiar with "operand read bypass", is this the same thing as "operand forwarding"? Is this a pipeline optimization? Might you have any link you could share on this?
  - thesz 8y ago
    It is the same thing. Just different name.

ngcc_hk 8y ago

The link assume you know and this as well. May be in both has a few short paragraph for those not in to appreciate and say thx you.

equalunique 8y ago

Shut up and take my money!

sitkack 8y ago

Wester Digital if you are reading this! Pleeeeze I want to have access as an end user. I'd like to do a predicate push down and be able to write into the DRAM buffer and the flush a commit. Or pin certain blocks directly into DRAM. Pleeeeze!

tyingq 8y ago
This person got pretty far with the Marvell ARM WD drive controller in 2015: https://www.malwaretech.com/2015/04/hard-disk-firmware-hacking-part-1.html https://www.malwaretech.com/2015/04/hard-disk-firmware-hacki... Also see: http://spritesmods.com/?art=hddhack&page=1 http://spritesmods.com/?art=hddhack&page=1
pkaye 8y ago
What would you use this for?

quinta1k 8y ago

It would be their dream come true if the hw oss community (very small) takes this up and develops it into something huge like for sw projects. There is so much manpower needed to develop these kinds of things - what better way than oss. However, too little, too late, ee industry. An entire generation of top tier college students have pretty much skipped ee.

jacoblambda 8y ago
Nowadays the Computer Engineering degree lets those of us who were torn between EE and CS get both. At least at Virginia Tech, CpE(Computer Engineering) easily outstrips CS and teaches the basics of CS and EE fundamentals as well as practical application of both of them.
- beatgammit 8y ago
  Sure, that makes sense in theory, but of the computer engineers I've known, they prefer one end or the other and aren't as good at either as someone dedicated to just one. However, this is a pretty small sample size (I helped interview at a small company), so I'm not sure if it's a trend.
  - jacoblambda 8y ago
    Ya most of us tend to prefer one side or the other but this system tends to be a good way to get create would be EEs with a decent bit of exposure to CS and vice versa. It doesn't create perfect mixed skills but give a working experience with both sides. For example I hate semiconductor work, dislike circuit analysis, and much prefer software but I enjoy working with VHDLs and embedded software. I'll take Rust or Haskell over Verilog any day but I have no problem working with VHDLs given the need.
    - deleted 8y ago
      [deleted]
gumby 8y ago

gmueckl 8y ago

So this is the logic of the controller in Verilog. But I don't see any test scripts. I am not an expert in logic design, but it seems to me that validation is at least as expensive and time consuming as the actual creation because you cannot afford mistakes in the ASIC masks. Am I missing something here?

noobiemcfoob 8y ago
https://github.com/westerndigitalcorporation/swerv-ISS https://github.com/westerndigitalcorporation/swerv-ISS
- KSteffensen 8y ago
  From a quick look this is a reference model, not a testbench. There is a lot of work needed, writing testbench environment, test cases, analyzing and writing coverage models etc. before the Verilog code can be considered verified and ready for ASIC tape-out. From my experience writing the design RTL code is at most 25% of the man hours. The rest is verification and some synthesis backend work.
sweden 8y ago
You are correct. The most difficult part of a design is not the design itself, it's all the documentation and the verification environment around it. This is a nice gesture but hardware is a bit different than software and dumping a bunch of RTL code is not really useful.
- noobiemcfoob 8y ago
  A full environment that could get you to a blinking LED off of an FPGA would be the complete dump, but I don't see the value in downplaying publishing a bulk of code that all others have hidden behind lock and key.

ksec 8y ago

How does it compare to BOOM [1], both RISC-V and both open source. [1] https://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom Edit: Not sure why I am getting downvoted, isn't this a valid question?

tyingq 8y ago
This one doesn't have out of order processing, a FPU, or a MMU. It's also 32 bit where BOOM is 64. Edit: There is a little more detail available for an existing Marvell ARM SATA controller (similar to what WD uses now), which this processor is probably the replacement for[1]. That indicates it has 2 ARM Cortex R4 cores. On the Cortex R4, it looks like the FPU is an optional feature, and there is no MMU, just an MPU[2]. Basically, it looks like the BOOM CPU is intended to be a general purpose CPU, and this is intended to be a very fast/capable microcontroller. It wouldn't run Linux, other than maybe something like uClinux. It does look to be potentially REALLY fast. See https://www.anandtech.com/show/13678/western-digital-reveals-swerv-risc-v-core-and-omnixtend-coherency-tech https://www.anandtech.com/show/13678/western-digital-reveals... [1] https://www.marvell.com/storage/assets/Marvell_88i9441_Soleil-H_pb_FINAL.pdf https://www.marvell.com/storage/assets/Marvell_88i9441_Solei... [2] https://developer.arm.com/products/processors/cortex-r/cortex-r4 https://developer.arm.com/products/processors/cortex-r/corte...
garmaine 8y ago
Because you’re comparing a workstation class out-of-order CPU design to a teeny tiny embedded chip lacking an FPU or even a unified code/data cache. It’s like saying “how does the Intel Atom compare against the AMD Ryzen Threadripper core?”
- TomVDB 8y ago
  Compared to the most other RV32 soft core implementations, this one is far from being teeny tiny!

zapdrive 8y ago

Is this code just for a processor, or an SOC? How is this different from the open source Shakti processor being designed by IIT Chennai?

xvilka 8y ago

Would have been awesome if they joined the effort of developing FIRRTL[1][2] and using it as a universal (LLVM-alike) hardware intermediate language, better suited modern chip design needs than Verilog or VHDL[3]. [1] https://github.com/freechipsproject/FIRRTL https://github.com/freechipsproject/FIRRTL [2] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/11/Reusability-is-FIRRTL-Ground-Izraelevitz.pdf https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/... [3] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19

diarmuidc 8y ago
A HDL that no one in the industry uses?
NotCamelCase 8y ago
It's a neat idea, but to me, that's like it. For SW, LLVM serves two-way: 1)target any (supported) arch you like with your language of choice, 2)customize your toolchain to generate native machine code (i.e. GPU shader langauges) from any (supported) language. I'd say putting yet another middleman between your logic compiler/netlist and what you actually use is not the best course of action for HW implementations. Even HLS has a big friction for use and is hardly picked up, with its obvious, immediate advantages.

glenrivard 8y ago

I am a bit older and seen a lot of tech come and go. RISC-V is something that feels like it is going to be really, really big. It has so much momentum so quickly.

nraynaud 8y ago

Can someone explain a bit what’s happening around the division? https://github.com/westerndigitalcorporation/swerv_eh1/blob/master/design/exu/exu_div_ctl.sv https://github.com/westerndigitalcorporation/swerv_eh1/blob/... Or give me some google keywords? Is there a link with the pentium bug?

yjftsjthsd-h 8y ago
This? https://en.m.wikipedia.org/wiki/Pentium_FDIV_bug https://en.m.wikipedia.org/wiki/Pentium_FDIV_bug Edit: This is just the top result from https://duckduckgo.com/?q=pentium+cpu+bug https://duckduckgo.com/?q=pentium+cpu+bug
- nraynaud 8y ago
  Link-> relationship
jhallenworld 8y ago
I like the small number case: they use a very old logic minimization program to generate the equations for it: https://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer https://en.wikipedia.org/wiki/Espresso_heuristic_logic_minim... Otherwise it's taking 32 cycles to do the division. There is a count for this.

Rochus 8y ago

Great work, many thanks to WD. As far as I see only a subset of the SystemVerilog features is used. Is there a "coding standard" somewhere available specifying this subset with a rationale? Is it mostly to be compatible with Verilator? Is there information available why they used Verilator and how it has proven itself?