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Open source RISC-V implemented from scratch in one night
- earenndil 8y agoThis is good news for risc-v! The fact that it can be implemented so easily by hobbyists furthers the cause of trusted hardware. Sure, it won't be implementable by hobbyists at the speeds necessary for modern desktop computing, but a trusted security core (something like a yubikey) could be implemented on completely from-scratch hardware, but then still use existing trusted/vetted software (openssl), just a cross-compile away.
- inetknght 8y ago"Modern" desktop computing is perhaps less resource hungry than you think when you cut away so much graft of telemetry. None or barely few games, of course. But word processing, email, and pure HTML browsing without javascript? Maybe not HTML5's fancy features, but general rich text? I think it's very achievable.
- moetech 8y agoThe web is incredibly bloated unfortunately. I had to upgrade my RAM recently because I couldn't open too many browser tabs without making the system hang, even with javascript disabled. Apart from that, you can do almost everything from the command line so even an old Raspberry Pi could be usable as a desktop computer.
- Erlich_Bachman 8y agoYou could still have a lot of RAM with RISC-V. The web does require lots of RAM nowadays, yes. But it is not a problem in this regard.
- h4b4n3r0 8y agoTake a look at Tab Wrangler extension. It closes tabs you haven’t used in a while.
- bogomipz 8y agoI am curious if you how how this compares to The Great Suspender? I also don't understand why Chrome and Firefox don't buil tab managers directly into the browser.
- opencl 8y agoFirefox used to have Tab Groups, it got removed but the webextension API got some new features specifically to support similar functionality in an extension. i.e. https://addons.mozilla.org/en-US/firefox/addon/basic-panorama/ https://addons.mozilla.org/en-US/firefox/addon/basic-panoram... In reality I think it's just not a priority for browser devs because the overwhelming majority of users do not use huge numbers of tabs.
- bogomipz 8y agoThanks. Yeah I suspect tab junkies are probably a minority. Do you know is the latest Firefox on par with Chrome in terms of tab usage and memory footprint?
- opencl 8y agoMemory usage in FF with lots of tabs seems a bit better than Chrome, CPU usage seems a bit worse. I think the UI does a significantly better job of handling them though, since Chrome just shrinks everything until there's no text left. About a year ago FF was really awful with lots of tabs, CPU usage was very high and the UI would occasionally freeze up for 10+ seconds at a time. They're really been making some big performance improvements lately.
- snaky 8y ago> pure HTML browsing without javascript I highly doubt this is achievable now. Turn on NoScript and vast majority of web sites just refuse to work not even properly, but to just load the content.
- inetknght 8y agoThen don't use shit websites that require javascript.
- ljj1122 8y ago... like my banks? I actually like/need to use websites that use javascript, imagine that
- userbinator 8y agoI wonder what the "vast majority" is that you mention. For me, with JS off by default, the majority of sites I come across when searching for things are perfectly readable without JS. The sites that need it are a small whitelist of ones I trust (e.g. the banks a sibling comment mentioned), which I enable. ...That said, a 75MHz RISC-V will be approximately comparable in performance to a 100MHz 486DX4, or a 40MHz Pentium.
- SmellyGeekBoy 8y ago> But word processing, email, and pure HTML browsing without javascript? Maybe not HTML5's fancy features, but general rich text? All things I've seen achieved on a 486... In fact, come to think of it, I've seen people doing all of the above on m68k-based systems too.
- simias 8y agoMy software "stack" hasn't changed in maybe 15 years now. It's emacs + firefox + terminal and a couple utilities here and there. It ran fine on my first computer with a single core ~1GHz CPU and 128MB of RAM (although multi-core architectures and more RAM did make it a lot easier to multi-task later). The only reason I upgrade my computer these days is to run modern games, for everything else except compilation I could probably use a computer from 10 years ago and not feel the difference. I'd gladly switch to a completely open source hardware architecture even if it meant losing a significant amount of raw performance provided that the hardware and OS are stable and it's not prohibitively expensive.
- noir_lord 8y agoThat sounds nice actually. I'm currently dealing with our legacy system which means I have multiple virtualised systems running in a replica of our production system. Currently using ~25 gig of RAM just to run the environments and an IDE.
- kilburn 8y agoI don't know what "prohibitvely expensive" is in your case, but there's a possibility today: Grab one HiFive Unleashed for $999 [1]: - 4 cores up to 1.5Ghz - 8Gb DDR4 ECC Ram - 1Gbps ethernet Then grab one HiFive Unleashed Expansion Board for $1,999 [2]: - SSD M.2 Connector - SATA3 Connector - x16 PCIE Connector (4 lanes of pcie2) - A bunch of other cool stuff you wouldn't probably use (SPI, FPGA, etc.) Finally grab some M.2 Drive and a graphics card ($500 maybe?). This would set you back a grand total of $3500, which is definitely way more expensive than the current mainstream but may fit within "non-prohibitively expensive" for some. The whole platform should be open source [3]. [1] https://www.crowdsupply.com/sifive/hifive-unleashed https://www.crowdsupply.com/sifive/hifive-unleashed [2] https://www.crowdsupply.com/microsemi/hifive-unleashed-expansion-board https://www.crowdsupply.com/microsemi/hifive-unleashed-expan... [3] https://www.sifive.com/products/hifive-unleashed/ https://www.sifive.com/products/hifive-unleashed/
- dtx1 8y agoWhile the hifive is an awesome proof of concept 3,5 k$ for essentially something performing roughly as well as a raspberry pi seems prohibitively expensive for now.
- AnIdiotOnTheNet 8y agoIt isn't the telemetry that's slowing us down, but layers upon layers of (mostly needless) abstraction and buffer bloat. Windows 95 had most of the things we use in a GUI environment today and it ran on a 486 with 8MB of ram. When packaged in Electron with a javascript x86 emulator it is still smaller than many modern text editors. Plenty of GUIs ran on significantly less. Since the modern web is basically one of the worlds most overengineered and crufty VM platforms, I don't expect it would run very well, and that would probably be enough to doom the system in the eyes of many, sadly.
- shawnz 8y agoWhat layers of abstraction are we stacking? Sure, there's electron/v8, but that's just one layer. You said yourself that notepad in an electron-based x86 VM is still pretty small, so clearly electron itself isnt the problem. Maybe people just demand more from their software these days, and all these little conveniences just add up more than you'd realize? That would also explain why the system is not "doomed in the eyes of many" as you claim it ought to be.
- belark 8y agoA lot of the conveniences of the modern computing landscape are anything but. Laggy response times in aforementioned text editors, frivolous UI animations on certain OSs, terrible web apps like JIRA... The complexity doesn't necessarily mean better software. It's quite often worse along many dimensions: performance, usability, maintainability, portability.
- rayiner 8y agoWhat conveniences? Most web apps (e.g. Google Docs) have less functionality than their Win95 counterparts, notwithstanding the stupendous amounts of added bloat.
- digi_owl 8y agoNever mind that Win95 didn't need a GPU that could push millions of polygons just to draw its UI...
- ddingus 8y agoThose things only require a couple hundred Mhz of general purpose computing to make sense. Maybe less, should specific purpose assists be available. And RAM address space sufficient to contain the tasks.
- samsoniuk 8y agoI think the best feature of the RISC-V instruction set is that is very clear and very simple. The RV32I instruction set is composed by ~40 different instructions and, depending of the environment and the implementation, you don't even need implement all them, as long the compiler will never generate some instructions. A simpler core means faster clock rates, less logic and more cores per chip, which much more performance. By this way, although the performance in the FPGA is not so good as in a ASIC, the results are not so bad: https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.23-Posters-Pub/HC29.23.p80-GRVI-Phalanx-Gray-GrayReserach-extd-abs.pdf https://www.hotchips.org/wp-content/uploads/hc_archives/hc29... With 1680 RISC-V cores running in parallel at 250MHz, the result is impressive, even working in a FPGA!
- josemanuel 8y agoWriting RTL takes one night but, how long will the verification take? How much will it take to tapeout? Who will pay for it?
- oddity 8y agoAs someone living in hardware land, I have a lot of respect for all the effort that goes into those steps of the process and I’m glad you brought it up, but presumably they aren’t that important to the point of a hobby project like this.
- geomark 8y agoAnother hardware lander here. Did a lot of verification of processors in the past, including one that was Mips-like. Parent comment is correct in its suggestion that verification is a much bigger deal than getting HDL that will compile and pass a few test cases. But for a hobby project, yeah, no need to throw a wet blanket on it.
- PhilWright 8y agoYour only comments on HN seem to be to criticize RISC-V. The posters intention is not to start producing hardware, at no point does his project mention taping it out and manufacturing. Obviously it is just a fun side project to implement the RISC-V core ISA in an FGA. It was then made open-source on GitHub so anyone else interested can look at it. Chill out mate.
- Annatar 8y ago"Your only comments on HN seem to be to criticize RISC-V." And in that, he's not alone: have you looked at RISC-V ISA? Compared to MC68000, it's exceptionally retarded, even more so when compared to OpenSPARC. Extremely dumb ISA.
- waterhouse 8y agoIf you named anything specific about the RISC-V ISA that you think is retarded, you might contribute something to the conversation.
- kbumsik 8y agoI don't know anything about RISC-V ISA yet, but I am wondering if its ISR is great for learning computer architecture in shcools compared to MIPS, the dominant ISR at colleges for introductory computer architecture classes? The HDL (Verilog) code looks quite short and simple. If the partial implementation of the ISR implementation is like that it shouldn't be so bad for learning...
- userbinator 8y agoIt's very similar to MIPS.
- xmo 8y agoYes. Berkeley started using it to teach introductory computer architecture: http://www-inst.eecs.berkeley.edu/~cs61c/sp18/ http://www-inst.eecs.berkeley.edu/~cs61c/sp18/ A major project of the course is to build RISVC emulator and implement 2-stage pipeline in logisim.
- kbumsik 8y agoWell Berkeley would certainly wants to teach RISC-V since Berkeley made that architecture. But it is still great to see they are actually using it in classes!
- henrikeh 8y agoThe technical university of Denmark also transistioned to teaching computer arch using RISC-V. Some of the most popular textbooks are also being converted to RISC-V editions.
- bogomipz 8y agoWow this is great! Do you or anyone else happen to know if any of the lecture videos for this course might be available online?
- bogomipz 8y agoWhat does ISR stand for in this context?
- lisk1 8y agoAs the possibilities for smaller transistor get narrower companies will get more open towards smaller clients with small budgets, so taping out homebrew CPUs or SOCs or integrated circuits will be possible.
- trumped 8y agoso far, the opposite is happening in the "cellphone"/pocket pc space... it is getting hard to get a phone that you can root without having to resort to "holes" that can get patched at any time...
- yipbub 8y agoCan you elaborate please?
- trumped 8y agoWell, most people aren't going to make their own chips any time soon... so you have to buy what is available and cellphones are getting more restricted/locked down everyday in the name of security (they are getting closer to what they used to be before Android came out)... not sure if that answers your question though.
- eight_ender 8y agoI love reading about stuff like this. There's something magical about having an inspiration fire so hot you can't put it out without 6 hours of hard coding at an ungodly hour.
- exikyut 8y agoI wonder how easy it would be to port https://github.com/xoreaxeaxeax/sandsifter https://github.com/xoreaxeaxeax/sandsifter to the RISC-V instruction set. Would probably be a decent step in the right direction for validating/verifying the future of trusted computing. Although... this gives rise to a 2nd thought. If it was _this easy_ to build a RISC-V implementation, is it all that special, technically speaking? I ask as someone naive about processor design. Is implementation relatively straightforward, but design hard?
- _chris_ 8y agoRISC-V is pretty nice in that the ISA gets out of your way, and you can focus on the techniques to build a high-performance processor without wasting effort on legacy and other weird corner case behaviors. A++, would recommend. However, if you want to build really high performance cores, there are plenty of challenging techniques you have to employ that add a lot of complexity that is hidden below the ISA abstraction layer (speculation for example). So if you want to make RISC-V go fast, you have to employ more design tricks like "macro-op fusion". For example, scan for two load instructions in the fetch stream and fuse them into a single "load-pair" micro-op if they access adjacent addresses. There are a whole bag of tricks like this that are irrespective of the ISA and add a fairly high "skill-ceiling" to processor design.
- renox 8y ago> RISC-V is pretty nice in that the ISA gets out of your way Except for the C variant where they went to 110% complexity for maximum ICache efficiency: 32bit instructions aligned to 16bit?? I wonder if there are other RISC ISA which made the same choice.
- phkahler 8y agoYes, while the C extension helps for high performance I think it feels like a major hack to instruction encoding. The RISC-V ISA does great with a very small number of instructions, so playing around with encodings is rather easy. I'm reaching the conclusion that fixed 24-bit opcodes are an close to optimal if immediate constants are allowed after.
- bem94 8y agoWhoa. This is very impressive! It does seem to hilight an increasing unease I have with riscv. Implementations are many and cheap, but reusable verification is rare and people don't use what is out there. They have maybe the riscv-tests set working. But that's not enough to call your new CPU usable for anything other than a hobby project. Fwiw, the riscv-formal package from Clifford wolf is the closest thing to a turn key solution to verifying a riscv core, even if people must remember it doesn't cover everything.
- samsoniuk 8y agohmmm... I promise investigate this topic in the future!
- deleted 8y ago[deleted]
- deeesa1 8y agoImpressive, I like this! I'm curious more in general how widely risc-v is being used in the industry today already (they mentioned a steep adoption from academia to industry). Looking at the foundation members, there are quite a big number; given they range for risc-v is from small devices to super computers, are there any examples where it's used today and showed benefits over other archs?
- Annatar 8y ago"The main motivation for the darkriscv is create a migration path for some projects around the 680x0/coldfire family." On the Amiga we don't need a replacement for MC680## processors because we have the Vampire 2+ accelerator, which gives us a superscalar, 64-bit MC68080 with AMMX extensions. Coming to ATARI ST and Amiga 1200 near you if the Apollo team keeps this momentum.
- samsoniuk 8y agoYeah, I know about it! But unfortunately the 68080 is too large for my FPGA applications, which are cost driven. Other open source 680x0 projects does not work too, by the same reason. For some years, I wondering how create a compact implementation of the 680x0 in the FPGA, but with no success. At some moment I started work in a subset of the 680x0, something like a RISC version of 68000, with a minimal instruction set and a very optimized pipeline, but in this case the problem moved to the toolchain and make the gcc work well is not so easy... Defeated by all that problems and limitations, I started test lots of new architectures and found the RISC-V.
- Annatar 8y agoWhat about OpenSPARC, since it has low power consumption and can be cut down to less cores and threads?
- samsoniuk 8y agoThe available implementation of the OpenSPARC is too complex: a single core with 4 threads requires 59350 LUTs and runs at 62.5MHz in a Virtex FPGA (according to [1], slide 21). Although is possible remove some features, I don't think is possible reduce the logic without impact the compatibility. I think the Leon3 [2] is a far better option for FPGAs, since requires only around 3500 LUTs and runs at 125MHz in a Virtex FPGA. In a low-cost FPGA, the performance of Leon3 is around 66MHz, which is enough to replace the 680x0 and coldfire v2 processors. The requirement for 3500LUTs is not so bad, as long the TG68 (an open source 68000 replacement in VHDL) has similar requirements. However, the typical RISC-V implementation uses less than 1/3 of the logic when compared with Leon3 and TG68. Also, although the RISC-V provides almost the same performance as the Leon3, the extra logic can be used for more parallel RISC-V cores, resulting in a increase of 2 or 3x in the total performance. Finally, there is an additional problem with OpenSPARC, Leon3 and TG68: the GPL license. In another hand, most RISC-V implementations use the BSD license, as long the RISC-V instruction set itself uses the BSD license. Of course, the OpenSPARC, Leon3 and TG68 are implemented that way. There is no obstacle, other than the technical complexity, to prevent develop a new OpenSPARC, Leon3 or TG68 from scratch, with a more firendly license, better performance or better use of the logic. In this case, the question is: how many time you need to implement a minimal viable core with one of that architectures? In the case of RISC-V is perfectly possible implement a small core in a FPGA with the RV32I instruction set in few hours, because the RV32I set of instructions is really very poor and primitive, which make it specially friendly to the hardware and explain why is so compact. [1] http://ramp.eecs.berkeley.edu/Publications/OpenSPARC%20T1%20on%20Xilinx%20FPGAs%20-%20Updates%20(Slides,%208-20-2008).pdf http://ramp.eecs.berkeley.edu/Publications/OpenSPARC%20T1%20... [2] http://ramp.eecs.berkeley.edu/Publications/LEON3%20SPARC%20Processor,%20The%20Past%20Present%20and%20Future.pdf http://ramp.eecs.berkeley.edu/Publications/LEON3%20SPARC%20P...
- mtgx 8y agoI wish open source projects would stop being hosted on the Microsoft-owned GitHub.
- Annatar 8y agoIf wishes were horses, beggars would ride.
- sergioisidoro 8y ago/rant "after one week of exciting sleepless nights of work (which explains the lots of typos you will found ahead), the darkriscv reached a very good quality result" Not commenting on the actual quality of the code, but I wonder how can one make typos due to sleep deprivation, and yet produce "good quality results" in software. I wonder when will we, as a community, stop praising all nighters and rushed work.
- geezerjay 8y ago> I wonder when will we, as a community, stop praising all nighters and rushed work. I agree, but it sounds like the author wanted to claim that he did something impressive in a small timeframe, thus suggesting to the reador some level of technical prowess. If the author claimed instead that he did it while well-rested in a couple of months then the achievement wouldn't be so impressive.
- tomhoward 8y agoThere's a big difference between doing short bursts of work with little sleep - particularly when you're young - vs doing it constantly for months/years. In this case it just seems to indicate enthusiasm for the project rather than dangerous overwork.
- samsoniuk 8y agoin fact: 50% enthusiasm for the project, 50% dangerous overwork! hehehe
- jacksmith21006 8y agoDid see that Google is using the RISC-V instruction set with their Pixel Visual Core processor. Here is an article and video on it. https://www.anandtech.com/show/13241/hot-chips-2018-the-google-pixel-visual-core-live-blog https://www.anandtech.com/show/13241/hot-chips-2018-the-goog...
- amelius 8y ago> works up to 75MHz How much would this increase if it used an ASIC instead of FPGA? And how much would it cost for different batch-sizes?
- wyldfire 8y agoIIUC it's critically dependent on the manufacturing process used. > how much would it cost A CPU IC isn't very interesting until it has some I/O, so it's much more meaningful to talk about an SoC with one or more of these darkriscv cores. Sorry, I don't have an answer other than to say "this isn't quite complete enough for it to be useful for most tasks." That said, there's probably tons of open source implementations of DDR/SPI/PCI/USB interfaces (on opencores.org, e.g.). So it's "only" a matter of integrating these.
- abfan1127 8y agofastest speeds depend on two things. First the manufacturing technology used (smaller is faster because parasitic capacitance is smaller, although finfet is getting to have large parasitic resistance). The 2nd factor is the datapath between flip flops. Some architectures handle very fast clock rates because the data path is simple (or pipelined). Others are quite slow. I've seen some architectures top out at 500MHz when another architecture is running over 1 GHZ in the same chip.
- Symmetry 8y agoQuite a bit in theory but memory latency wouldn't decrease so there would have to be some added complexity in interfacing with it.
- samsoniuk 8y agoWell, I tested three different configurations for memory: darkriscv@75MHz cache=off 0-wait-states 2-stage pipeline 2-phase clock: 6.40us darkriscv@75MHz cache=on 3-wait-states 3-stage pipeline 1-phase clock: 9.37us darkriscv@50MHz cache=on 3-wait-states 2-stage pipeline 2-phase clock: 13.84us The first configuration works in a zero wait-state environment with separate instruction and data high speed synchronous memories working in a different clock phase (weeeeeird!). As long there are no latency, this configuration works at 75MIPS with a 2-stage pipeline, which means only one clock is lost when the pipeline is flushed by a branch. The second configuration uses a small hi-speed cache with 256 bytes for instruction and 256 bytes for data, a 3-stage pipeline, which means two clocks are lost when the pipeline is flushed by a branch and a more convencional single phase clock architecture, as well a memory with 3 wait states or something like this. Although working at 75MIPS, the cache miss and the longer pipeline decrease the performance to around 51MIPS. The third configuration is the core configuration from the first scenario, but with the small hi-speed cache from the second scenario and the 3 wait states. In this configuration, the performance decreased to 50MHz and, according to my calculations, the performance is around 34MIPS. By this way, if is possible work only with the interna FPGA memory, the first configuration is better, otherwise you can use the second configuration. I guess is possible create a fourth configuration with the 3-stage pipeline and zero wait-states (no cache), but I need implement a two-clock load instruction. In this case, I guess is possible peak around 100MHz.
- wyldfire 8y ago> and the best feature: BSD license IIRC this isn't the first open source RISC-V core but it's great to see another implementation.
- samsoniuk 8y agoIt is not even the first RISC-V with BSD license, but I love make some GPL friends cry! ;D
- akuma73 8y agoSorry to burst any bubbles here, but this is s very incomplete implementation. You couldn’t run anything but small toy programs on this machine. This is more like what a student would build in an undergraduate course in computer architecture. For example, there is no MMU, no debug support, no traps, no interrupts, no exception handling, no OS privledge levels, no FP, no memory controller etc. Of course, one wouldn’t implement all of these in a few hours. The fact that this is RISCV is somewhat of a red herring as you could do a similar thing with a restricted subset of MIPS or ARM or even x86 as they do in UT Austin’s comp arch class.
- OnlyRepliesToBS 8y agohahaha
- hesdeadjim 8y agoThat class was one of my favorites at UT. I was lucky enough to have a guy from Intel teach it as an adjunct.
- amelius 8y agoWhat book did you use?
- hesdeadjim 8y agoIt’s been about 14 years so not entirely sure. The textbook was using a RISC architecture from what I remember. We also had a semester long project where we had to research and invent a new x86 instruction to speed up a program of our choice. It was... intense.
- aappleby 8y agoAn Arduino has none of the missing parts you mention (except interrupts), yet it's quite a useful device even in non-toy applications.
- 8y ago
- adiusmus 8y agoCould be fun in near future. Plenty of room for improvement so it’s a good base for exploration of Fpgas. And with this https://bellard.org/riscvemu/ https://bellard.org/riscvemu/ and similar projects already spun up in other ways, risc-v is becoming more interesting as time goes by.
- samsoniuk 8y agowow! I didn't expect to get so many comments and questions about my weird project! thank you all! :)