samsoniuk

4 ms·

1.
FPGA Pin Finder(github.com)
1 points by samsoniuk 5y ago|1 comments
2.
by samsoniuk 5y ago
The project goal is identify some missing pins from the Storey Peak Stratix V FPGA board, but can be used widely with other recycled FPGA boards! The concept is very easy: build an FPGA image that periodically send a UART string with the re
3.
by samsoniuk 8y ago
The available implementation of the OpenSPARC is too complex: a single core with 4 threads requires 59350 LUTs and runs at 62.5MHz in a Virtex FPGA (according to [1], slide 21). Although is possible remove some features, I don't think
4.
by samsoniuk 8y ago
Almost! For most of time I work only in the simulator (Xilinx ISIM), but luckily I have lots of FPGA boards available at work too!
5.
by samsoniuk 8y ago
After two weeks, I hope most critical problems are already solved, as long more complex software is working without problems, thanks to the clear and simple RV32I instruction set! Of course, as observed in the project description, I am work
6.
by samsoniuk 8y ago
Yeah, I know about it! But unfortunately the 68080 is too large for my FPGA applications, which are cost driven. Other open source 680x0 projects does not work too, by the same reason. For some years, I wondering how create a compact implem
7.
by samsoniuk 8y ago
in fact: 50% enthusiasm for the project, 50% dangerous overwork! hehehe
8.
by samsoniuk 8y ago
Well, I tested three different configurations for memory: darkriscv@75MHz cache=off 0-wait-states 2-stage pipeline 2-phase clock: 6.40us darkriscv@75MHz cache=on 3-wait-states 3-stage pipeline 1-phase clock: 9.37us darkriscv@50MHz cache=on
9.
by samsoniuk 8y ago
I am not sure is recommendable integrate this design in a ASIC because is not so stable yet, but the synthesis tool pointed 133MHz in a Xilinx Artix-7 FPGA, running at 1 clock/instruction. A more pipelined and stable RISC-V design, suc
10.
by samsoniuk 8y ago
hmmm... I promise investigate this topic in the future!
11.
by samsoniuk 8y ago
I think the best feature of the RISC-V instruction set is that is very clear and very simple. The RV32I instruction set is composed by ~40 different instructions and, depending of the environment and the implementation, you don't even
12.
by samsoniuk 8y ago
Good point, but unfortunately the focus of the project is only the RISC-V core running in a FPGA. Everything else is already widely available in the internet and can be easily integrated.
13.
by samsoniuk 8y ago
It is not even the first RISC-V with BSD license, but I love make some GPL friends cry! ;D
14.
by samsoniuk 8y ago
I fully agree with you about the missing features! However, as long my objective is replace some legacy 680x0/683xx/coldfire processors running small toy programs, I see no need for that complex features. Please keep in mind that
15.
by samsoniuk 8y ago
wow! I didn't expect to get so many comments and questions about my weird project! thank you all! :)