28 ms·

Why Use an FPGA Instead of a CPU or GPU?

284 points by ScottWRobinson 8y ago

deleted 8y ago
[deleted]
rini17 8y ago
Is there high performance FPGA that does not depend on proprietary bloated windows-only toolchain?
- opencl 8y ago
  Every FPGA I have used has offered their proprietary bloated incredibly expensive toolchain on Linux. There's icestorm but the supported hardware is not exactly high performance, IIRC the biggest chips supported have around 8K LUTs.
  - baobrien 8y ago
    The proprietary bloated toolchains are free to use for lower end to mid range parts, even on Linux.
    - opencl 8y ago
      Yes but as as soon as you hit the limits of i.e. Quartus Lite it's $4k per seat per year. Then another $2k for Modelsim. And another $2k if you want the DSP package, etc.
      - FPGAhacker 8y ago
        That's on the super low end of the price spectrum.
- radarsat1 8y ago
  Proprietary and bloated yes, but I believe both Xilinx and Altera both have software available for Linux, or am I wrong? At least I used Altera's suite on Linux once for a pilot project.
  - jeffreyrogers 8y ago
    I have used Xilinx's toolchain on Linux, though it was hard to get working. This was a few years ago.
    - slededit 8y ago
      They support Ubuntu now. Setup was just as easy as windows for me.
  - duck2 8y ago
    I recently installed Altera Quartus on Debian for a school project. It kept crashing after 2 seconds. First result on google says quartus uses its own libcurl which is broken and you should copy the OS libcurl to /opt/altera/quartus/lin64/lib/whatever. Lots of issues like this.
- asandweech 8y ago
  Last time I checked, vivado was available and fully functional on linux. Unless you are aware of a change in the last few minutes?
- lvoudour 8y ago
  All vendors have linux toolchains. But they are still proprietary and bloated (at least after a point)
- plasticchris 8y ago
  There's vivado on Linux and the open source toolchain for some lattice fpgas (icestorm)
- rwmj 8y ago
  Supposedly some of the Xilinx 7 series FPGAs have been reverse engineered so there is a possibility of supporting them in Yosys (which is reasonable free toolchain). I've not been able to get much information about this, but you can check on the website: http://www.clifford.at/yosys/ http://www.clifford.at/yosys/
  - striking 8y ago
    From the FAQ at http://www.clifford.at/yosys/faq.html http://www.clifford.at/yosys/faq.html: > 2. What synthesis targets are supported by Yosys? > Yosys is retargetable and adding support for additional targets is not very hard. At the moment, Yosys ships with support for ASIC synthesis (from liberty cell library files), iCE40 FPGAs, Xilinx 7-Series FPGAs, Silego GreenPAK4 devices, and Gowinsemi GW1N/GW2A FPGAs. > Note that in all this cases Yosys only performs synthesis. For a complete open source ASIC flow using Yosys see Qflow, for a complete open source iCE40 flow see Project IceStorm. Yosys Xilinx 7-Series synthesis output can be placed and routed with Xilinx Vivado. [emphasis mine]
- orbifold 8y ago
  Actually the EDA industry for the longest time only hard working versions of their tools for "esoteric" cpu architectures like the Sparc and Solaris :). So yes by now they do support linux very well, some of the cadence and synopsis tools might not even work on windows (you need them for simulation, when Modelsim does not cut it). In any case EDA has been a Unix / Linux domain because it is so old and used to require really expensive unix workstations.
- e12e 8y ago
  I believe this was on hn recently (uses icestorm as mentioned by others): http://www.excamera.com/sphinx/article-j1a-swapforth.html http://www.excamera.com/sphinx/article-j1a-swapforth.html
antoineMoPa 8y ago
"Intel does offer an emulator, so testing for correctness does not require this long step, but determining and optimizing performance does require these overnight compile phases." After some experience with FPGAs, the emulation step is not enough to test for correctness. Most of the problems happen while synchronizing signals with inputs/outputs and with other weird timing problems, glitches and unintuitive behavior that FPGAs provide (and the emulator behaves differently). I was using VHDL however. Anybody has experience with OpenCL on FPGAs to explain what difficulties persist (are the timing problems easier to solve)?
- shriver 8y ago
  There are a number of real issues with the emulation approach even now. Firstly, emulation isn't accurate - if you do floating point math in your application it will give you different results (within the tolerances of the OpenCL spec) on FPGA vs. CPU. So you can't test for correctness in the emulator. A second more serious issue is that getting performance that justifies using an FPGA requires tuning very carefully to the architecture. This may mean adopting pipeline architectures that destroy emulator performance (there's still issues with the emulator identifying that the design patterns for shift registers in FPGA look like pointer fun on CPU rather than mammoth memcpys). So for a huge part of the design stage the emulator is basically useless- because it tells you nothing about what you care about, since the performance of the emulator is often negatively correlated with performance on FPGA. This is made worse if you're doing hardcore FPGA tricks like mixed precision arithmetic. As you say though - the fact that timing is lost in the emulator also means you don't get a true idea of whether you have buffer overflows etc or lock-up. Adding debug into the actual design impacts the implementation on FPGA in a way that it doesn't for software - and is sometimes unintuitive.
  - pjc50 8y ago
    > if you do floating point math in your application it will give you different results That seems like a gross weakness in the emulator; floating point isn't actually nondeterministic!
    - 8y ago
deleted 8y ago
[deleted]
rwmj 8y ago
I'm surprised he doesn't talk much about direct cost (rather than engineering cost). A decent FPGA developer kit will cost several thousands of US$, more expensive even than high end GPUs.
- lightbyte 8y ago
  You can buy this dev board to play around with and learn FPGA for $75, and it has extensive documentation and resources to help you https://www.sparkfun.com/products/11953 https://www.sparkfun.com/products/11953
  - rwmj 8y ago
    But that's not a high performance FPGA. Believe me, I have a ton of FPGAs at home (starting even cheaper than that), and I write about them all the time: https://rwmj.wordpress.com/?s=fpga https://rwmj.wordpress.com/?s=fpga However if you're doing the sort of work which isn't just hobbyist stuff, you're going to spend 1000s on a board. This is the sort of thing commercial developers will be using: https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-...
    - lightbyte 8y ago
      If you're building a commercial product, a 3k dev board sounds incredibly cheap. My company spends orders of magnitudes more on licenses for an IDE extension (resharper).
      - rwmj 8y ago
        Absolutely. However I guess you'll also want to deploy your FPGA application at some point, which means buying FPGAs for all your servers too. So the cost is more analogous to the cost of a CPU/GPU than to the cost of an IDE/developer license.
    - FPGAhacker 8y ago
      You can get boards with a zynq 7020 on them for less than $200.
jaxtellerSoA 8y ago
Aren't FPGA's used mostly to test/design a circuit that you would then go on to actually fabricate/build? I could be wrong but I thought FPGA's were stateless (meaning if they powered off/reboot you loose everything and have to set it up from scratch again).
- zwieback 8y ago
  Yes and yes but new uses are emerging, it's like 3D printing: there's a crossover where the extra cost you pay for flexibility becomes too much to compete with hard wired logic despite the high initial cost.
  - monocasa 8y ago
    To be fair, it's not new. People have been using FPGAs in that capacity for decades.
    - zwieback 8y ago
      Very true, but mostly EEs and embedded SW/FW engineers. I think the SW tools, although still awful, are reaching the point where more SW-focused developers can take advantage of FPGA flexibility. Which isn't to say every programmer shouldn't be forced to struggle through a Verilog or VHDL project - that'll put some hair on your chest and the fear of god into you. I'll see your async and raise you an "always @(posedge clk)"
- stumpylog 8y ago
  No, they retain state. We used an Altera DE1 in school and it retained our burnt in program until erased or reprogrammed
  - zwieback 8y ago
    Probably burned into an external EEPROM or flash, the FPGA fabric itself still has to be configured by some external means. It's pretty fast but on-the-fly reprogramming of the FPGA logic is still an issue where you want to very quickly switch the logic on the FPGA.
amelius 8y ago
One reason could be to meet real-time constraints or to get predictable timing. This is becoming more and more difficult to do with modern CPUs for all sorts of reasons.
nastypasty 8y ago
Whats that for?
mladmon 8y ago
"...programming FPGAs is still an order of magnitude more difficult than programming instruction based systems." True statement. If you're offloading computation from a CPU, profile your application first, and determine if the FPGA board's architecture will allow you to improve performance. Don't underestimate the cost of communicating data to/from the FPGA/CPU.
petra 8y ago
I doubt that programming efficiency is what's holding back FPGA's for general compute. Why ? because we've seen decades of research in this area - so at least we have some tools(c for fpga isn't ideal, but still...), and a lot of the general mapping between what algorithms should be in FPGA. And Amazon FPGA's instance exist for over a year. So in that time, if there worth while services to offer with FPGA's, people would have offered them, or at least started. And sure programming complexity is a barrier. but entrepreneurs and VC's love competitive barriers. So where's all this VC funding going towards this area ? Where are all those startups ?
- seliopou 8y ago
  I disagree. FPGA design remains a highly-specialized area. Tools such as VivadoHLS, and other high-level synthesis tools, do provide some improvement in productivity though with inherent tradeoffs in design quality. There's been a lot of new hardware construction language popping up recently (e.g., HardCaml--which I happen to use, Chisel, Migen, PyMTL, etc.). They may bring something to the table in the coming years, but that's yet to be determined. HardCaml's pretty great though, IMHO. But then again I'm already biased towards OCaml, and I get to work with its creator!
- amirhirsch 8y ago
  Disagree. I worked in this space for 15 years and watched CUDA win a market for NVidia that was ripe for the picking by Xilinx or Altera. The culture around hardware design prototyping dominates the FPGA field and all attempts at making it approachable by software development are stunted by the proprietary ecosystem. I also think that high level synthesis is largely misguided since sequential imperative style isn't the correct way to think about FPGAs and also doesn't really address the lack of a good low-level language with an abstraction mechanism, and fundamental need for an operating system for running processes on a reconfigurable computing system.
Firerouge 8y ago
I've always thought FPGAs would be perfect to have hardware backed video decoding/encoding that could adapt to new codecs (like vp9) while also being updatable for new performance improving discoveries. It also seemed like it would go well with a generic radio subsystem, so you could compile hardware support for new wireless standards that come out after your hardware did (essentially an fpga sdr). It seems like there could be lots of uses for being able to on demand enable hardware acceleration for certain tasks a program might need lots of.
- jakeinspace 8y ago
  I spent this summer doing exactly that for an internship. I set up a xilinx Zynq chip to run a basic video capture and streaming program (based on gstreamer), with the encoding portion handled by the fpga. This chip has a baked-in encoder supporting AVC and HEVC, but I suppose you could implement or buy your own IP block for other codecs. Xilinx makes multiple boards based off the same chip with support for video codecs and SDR.
- mirashii 8y ago
  FPGAs are indeed commonly used for SDR as well. Ettus has a range of USRPs with FPGAs on-board, and you can find readily available IP cores for anything from Bluetooth to DVB-S.
  - Firerouge 8y ago
    That's partially where I got my inspiration. Seems like it integrated properly it could be a great component in a general purpose PC to future proof it against changing needs and requirements
- zymhan 8y ago
  Experience seems to show that standardizing on a codec or instruction type is the most likely path. Apple iDevices have had hardware transcoding for video for a couple releases now. You really can't just have an FPGA that you recompile to a different architecture within a split second. They typically require compiling, downloading, and testing the the architecture you're deploying. Until someone comes up with a much faster to deploy FPGA, you'll likely not see enough efficiency gains in having a codec-specific processor given the time it takes to reconfigure the FPGA for each codec.
dojopico 8y ago
Another FPGA sweet spot is analyzing TB/PB-scale databases. Netezza programmed FPGAs to uncompress, project, restrict (including NULLs), enforce isolation & visibility and check CRCs at disk scan rates (>200MB/sec). When touching a handful of columns from a 20-200 column table, CPUs spend most of their time stalled on cache line misses. FPGA-projecting just those few columns into memory enormously increases cache hit rates.
- paulsutter 8y ago
  Plain C code can readily scan at a couple GB/sec on an ordinary Intel core, and NVME drives can transfer 8 or 16GB/sec
floatboth 8y ago
> An exception to the rule that GPUs require a host is the NVidia Jetson, but this is not a high-end GPU Well, the host is just on the same die, but it's still there
godber 8y ago
One interesting use case for FPGAs is where hardware qualification is very expensive, for instance for use in space. If a given FPGA is already space qualified, you just need to load new code onto it and you can skip the expensive qualification step for your new application. You can also consolidate functionality of multiple chips into that one qualified FPGA.
- irq-1 8y ago
  The expense for space is producing RAD Hard parts. (The designs are done on the same FPGA then a few RAD Hard chips are made.) https://en.wikipedia.org/wiki/Radiation_hardening https://en.wikipedia.org/wiki/Radiation_hardening
seliopou 8y ago
One clarification on the comment about latency. FPGAs are typically clocked much slower than a modern CPU. Typically, they run somewhere in the low 100's of MHz, whereas an Intel CPU clocks in at around 3GHz last time I went to the Apple Store. With a typical x86 multiply instruction having a latency of about, say, 3 cycles, putting that workload on an FPGA would result in a ~10x slow-down! The real benefit of an FPGA is that you get to decide what happens in any given cycle. So rather than being able to multiply two numbers in a single cycle like on x86, you could make your FPGA design do, say, 20 multiplications in a single cycle (space allowing). Which means that you can now multiply 20 numbers in 1/10th of the time it would take on x86. (In reality I think you have something like four execution units capable of perfoming parallel ALU operations per cycle, depending on the family.) So the latency benefit of an FPGA comes from flexible, almost (almost) unbounded potential for parallelism in a given cycle, not clock frequency. Hardware has to be designed to exploit this potential, otherwise it's not going to see any improvement in latency. Anyways, just something that is maybe obvious once you're told it, but isn't always mentioned in discussions like this. It certainly something that I didn't fully appreciate before getting involved in hardware design.
- pensono 8y ago
  FPGA latency is also much more predictable. Since you have cycle level control, you can know exactly how long any given operation will take. In a multi-threaded CPU, it's likely that the operation may be interrupted or delayed because of another process using the same resourt. It's also worth noting that FPGAs are often much closer to the I/O than a CPU on a motherboard. Pin to pin latencies are much reduced in a situation where direct access to I/O is available. An Ethernet stack can sit on the same silicon without having to serialize data between the CPU and the north bridge.
  - 0xffff2 8y ago
    >In a multi-threaded CPU, it's likely that the operation may be interrupted or delayed because of another process using the same resourt. If you're considering an FPGA, isn't the alternative likely bare-metal CPU programming? In that case, you have just as much control over thread scheduling as you do over FPGA timing don't you?
ChuckMcM 8y ago
The author isn't aware apparently of over a decade of work done in FPGA/CPU integration. Both in more sequential languages like System C[1] or in extended instruction set computing like the Stretch[2]. Not to mention the Zynq[3] series where the CPU is right there next to the FPGA fabric. For "classic" CPUs (aka x86 cpus with a proprietary frontside bus and southbridge bus) it can be challenging to work an FPGA into the flow. But the problem was pretty clear in 2007 in this Altera whitepaper[4] where they postulate that not keeping up with Moore's law means you probably end up specializing the hardware for different workloads. The tricky bit on these systems is how much effort/time it takes to move data and context between the "main" CPU and the FPGA and then back again (Amdahl's law basically). When the cost of moving the data around is less than the scaling benefit of designing a circuit to do the specific computation, then adding an FPGA is a winning move. [1] https://www.xilinx.com/products/design-tools/vivado/prod-advantage/rtl-synthesize.html https://www.xilinx.com/products/design-tools/vivado/prod-adv... [2] http://www.stretchinc.com/index.php http://www.stretchinc.com/index.php [3] https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html https://www.xilinx.com/products/silicon-devices/soc/zynq-ult... [4] https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01029.pdf https://www.intel.com/content/dam/altera-www/global/en_US/pd...
- blacksmythe 8y ago
  >> The tricky bit on these systems is how much effort/time it takes >> to move data and context between the "main" CPU and the FPGA and then back again The sweet spot for FPGAs is when the data is streaming. You can build hardware where the data is passed from one stage to another, and doesn't go to RAM at all. Particularly where the data is coming in fast, but with low resolution (huge FPGA advantage for fixed point instead of floating point). FGPAs are much more efficient for signal processing from data collected from an A/D converter (e.g. software defined radio) or initial video processing from an image sensor.
  - tomnipotent 8y ago
    > The sweet spot for FPGAs is when the data is streaming Netezza does this with their hardware, I've been dreaming of the day I could DIY and put a OSS RDBMS on top.
stevesimmons 8y ago
Does anyone have experience of Reconfigure.io [1] and their toolchain that transpiles Go for execution on FPGAs [2]? I am curious how it feels from the developer perspective, how it works in practice, and what types of applications it is a good fit for. [1] https://reconfigure.io https://reconfigure.io [2] http://docs.reconfigure.io/overview.html http://docs.reconfigure.io/overview.html
- zackmorris 8y ago
  I've waited 20 years for something like that, thanks for posting! FPGAs are great but I think the biggest problem with them is that they're an array of gates instead of logic units (like ALUs). So the learning curve to get to the point where you can place an array of cores and memories and have them all communicate is so high that most people never get that far. So that's been a huge barrier to exploring the problem spaces that GPUs are currently used for like AI and physics simulations. Hopefully using languages like Go/Elixer/Erlang/MATLAB/Octave etc will alleviate that to some degree. My gut feeling is that in 3-5 years we'll reach the limits of what SIMD can accomplish and we'll find it difficult to do the kinds of general-purpose MIMD computing needed to move beyond the basic building blocks of AI like neural nets and genetic algorithms. I stumbled onto these links a month and a half ago and I think something like this will make writing generalized/abstract highly parallelized code tractable again: http://aggregate.org/MOG/ http://aggregate.org/MOG/ https://en.wikipedia.org/wiki/Flynn%27s_taxonomy https://en.wikipedia.org/wiki/Flynn%27s_taxonomy Original at: https://news.ycombinator.com/item?id=17419917 https://news.ycombinator.com/item?id=17419917
- monocasa 8y ago
  It's so far outside the model of FPGAs, that I wouldn't even consider putting in the effort. It's like how regular code doesn't run well on the GPU, but much worse.
- zymhan 8y ago
  Unless you have optimized your code as much as possible to run on x86 or GPU and still find that you need a prohibitively expensive amount of processing power to accomplish the task, then and only then is an FPGA worth it. It is literally a DIY CPU architecture. So, unless you know exactly what it is about your current CPU's architecture that is holding you back, you won't be able to benefit from an FPGA-based design.
make3 8y ago
Is there a pipeline to compile tensorflow computation graphs to fpga? seems like this is one possible benefit of Tensorflow's fixed graphs, that they may be much easier to compile to fpga then other options Edit: Seems like some experimental work is being done with XLA (and llvm) https://www.google.ca/amp/s/www.nextplatform.com/2018/07/24/clearing-the-tensorflow-to-fpga-path/amp/ https://www.google.ca/amp/s/www.nextplatform.com/2018/07/24/...
foobaw 8y ago
What are some cool jobs for FPGA experts besides Intel and Military? It seems like there's not much availability.
- kurtisc 8y ago
  I recently spoke to someone at Broadcom who was moving networking processes from software to hardware using them, try looking into similar companies.
- pkaye 8y ago
  Lots of companies who design ASICs will prototype them on FPGA for catching bugs and start early firmware development.
- kingosticks 8y ago
  In the past I've seen job adverts for networking companies (routers) and hedge funds. Not sure if either of them count as cool.
neuromantik8086 8y ago
> The HPC community is already used to GPUs — getting people to switch from GPUs to FPGAs requires larger benefits. It's worth pointing out that some scientists haven't even made the leap to CPGPU computing yet and are still relying upon OpenMP / multithreading on general purpose CPUs, even when a GPU would be clearly superior. Anecdotally, I remember hearing that climate science simulations are particularly bad about taking advantage of new architectures for speedups, an assertion which possibly is supported by the fact that climateprediction.net simulations took several days using all 8 cores on my laptop to finish. Neuroimaging is also pretty bad, since other than Broccoli [0], most toolkits for preparing analyses don't leverage GPUs, even though I'd wager 80% of the steps involved image manipulations / linear algebra. [0] https://github.com/wanderine/BROCCOLI https://github.com/wanderine/BROCCOLI
- cjhanks 8y ago
  In my experience, it's true. And it's unlikely to change - the simulation code was largely written in FORTRAN and C over a period of 50 years. This is in fact what makes Intel Phi so appealing to some.
  - amirhirsch 8y ago
    12 years ago I worked on High Level Synthesis at Xilinx converting atmospheric moisture simulations from FORTRAN...
  - nl 8y ago
    For C/Fortran using LAPACK it should be as simple as relinking. https://www.olcf.ornl.gov/tutorials/gpu-accelerated-libraries/ https://www.olcf.ornl.gov/tutorials/gpu-accelerated-librarie...
- fulafel 8y ago
  I think these scientists are the real winners. Computers just work for them, they don't need to jump through hoops - eg, rewrite their software for immature proprietary software architectures. Chasing that last 10x of performance at great cost is for the desperate!
- 8y ago
saagarjha 8y ago
Is it just me, or does this article seem like it’s trying really hard to push Intel? For an article about FPGAs, failing to acknowledge the other (major) player in the market-there’s no mention of Xilinx anywhere in the article, while plenty of Intel/Altera-seems disingenuous. Really, the tone just seemed to stick out to me as an subtle advertisement piece; maybe it’s just me?
faragon 8y ago
I would love to see projects like MAME and MESS targeting FPGA hardware for near-perfect hardware emulation of classic hardware.
- IvanGoneKrazy 8y ago
  The Anologue Super Nt project uses an FPGA to run SNES cartridges unemulated. https://www.analogue.co/pages/super-nt/ https://www.analogue.co/pages/super-nt/
  - faragon 8y ago
    But it is not Open Source. There are more commercial products using FPGA's for emulating gaming console hardware.
jwbensley 8y ago
"A couple of FPGAs in mid-air (probably)"
hyperpallium 8y ago
How long does it take to "program" a FPGA? i.e. compared with typing a command, and having it load into memory. What about a JIT that compiles hot code sections to FPGA? (Though compilation sounds too slow) EDIT "one or two seconds or at least 100's of milliseconds." https://electronics.stackexchange.com/questions/212069/how-long-to-program-a-fpga-seconds-microseconds-less https://electronics.stackexchange.com/questions/212069/how-l...
exabrial 8y ago
Why does the compilation take hours, is this an NP Hard problem?
- mmirate 8y ago
  If my memory of a Processor Design course is correct, arranging the desired functionality onto the finite resources of an actual FPGA chip, let alone in such a way as to get good performance (i.e. have critical paths be as short as possible), reduces to bin-packing.
  - esfandia 8y ago
    The answer might be obvious, but I'm not a hardware guy: couldn't they use a FPGA to do the compilation itself, or at least the bin-packing part? Is there a way to code a general SAT-solver in FPGA?
tzs 8y ago
For those wanting to play around with an FPGA, this looks quite interesting: https://www.sparkfun.com/products/14829 https://www.sparkfun.com/products/14829 It's about half the price of the other FPGAs I've seen commonly used for hobbyist projects [1], doesn't need any separate programmer board to interface to your computer for programming, and has an open source tool chain available. I've not played with it, as it just showed up in a mailing from Sparkfun about new products. [1] such as https://www.sparkfun.com/products/11953 https://www.sparkfun.com/products/11953

deleted 8y ago

[deleted]

rini17 8y ago

Is there high performance FPGA that does not depend on proprietary bloated windows-only toolchain?

opencl 8y ago
Every FPGA I have used has offered their proprietary bloated incredibly expensive toolchain on Linux. There's icestorm but the supported hardware is not exactly high performance, IIRC the biggest chips supported have around 8K LUTs.
- baobrien 8y ago
  The proprietary bloated toolchains are free to use for lower end to mid range parts, even on Linux.
  - opencl 8y ago
    Yes but as as soon as you hit the limits of i.e. Quartus Lite it's $4k per seat per year. Then another $2k for Modelsim. And another $2k if you want the DSP package, etc.
    - FPGAhacker 8y ago
      That's on the super low end of the price spectrum.
radarsat1 8y ago
Proprietary and bloated yes, but I believe both Xilinx and Altera both have software available for Linux, or am I wrong? At least I used Altera's suite on Linux once for a pilot project.
- jeffreyrogers 8y ago
  I have used Xilinx's toolchain on Linux, though it was hard to get working. This was a few years ago.
  - slededit 8y ago
    They support Ubuntu now. Setup was just as easy as windows for me.
- duck2 8y ago
  I recently installed Altera Quartus on Debian for a school project. It kept crashing after 2 seconds. First result on google says quartus uses its own libcurl which is broken and you should copy the OS libcurl to /opt/altera/quartus/lin64/lib/whatever. Lots of issues like this.
asandweech 8y ago
Last time I checked, vivado was available and fully functional on linux. Unless you are aware of a change in the last few minutes?
lvoudour 8y ago
All vendors have linux toolchains. But they are still proprietary and bloated (at least after a point)
plasticchris 8y ago
There's vivado on Linux and the open source toolchain for some lattice fpgas (icestorm)
rwmj 8y ago
Supposedly some of the Xilinx 7 series FPGAs have been reverse engineered so there is a possibility of supporting them in Yosys (which is reasonable free toolchain). I've not been able to get much information about this, but you can check on the website: http://www.clifford.at/yosys/ http://www.clifford.at/yosys/
- striking 8y ago
  From the FAQ at http://www.clifford.at/yosys/faq.html http://www.clifford.at/yosys/faq.html: > 2. What synthesis targets are supported by Yosys? > Yosys is retargetable and adding support for additional targets is not very hard. At the moment, Yosys ships with support for ASIC synthesis (from liberty cell library files), iCE40 FPGAs, Xilinx 7-Series FPGAs, Silego GreenPAK4 devices, and Gowinsemi GW1N/GW2A FPGAs. > Note that in all this cases Yosys only performs synthesis. For a complete open source ASIC flow using Yosys see Qflow, for a complete open source iCE40 flow see Project IceStorm. Yosys Xilinx 7-Series synthesis output can be placed and routed with Xilinx Vivado. [emphasis mine]
orbifold 8y ago
Actually the EDA industry for the longest time only hard working versions of their tools for "esoteric" cpu architectures like the Sparc and Solaris :). So yes by now they do support linux very well, some of the cadence and synopsis tools might not even work on windows (you need them for simulation, when Modelsim does not cut it). In any case EDA has been a Unix / Linux domain because it is so old and used to require really expensive unix workstations.
e12e 8y ago
I believe this was on hn recently (uses icestorm as mentioned by others): http://www.excamera.com/sphinx/article-j1a-swapforth.html http://www.excamera.com/sphinx/article-j1a-swapforth.html

antoineMoPa 8y ago

"Intel does offer an emulator, so testing for correctness does not require this long step, but determining and optimizing performance does require these overnight compile phases." After some experience with FPGAs, the emulation step is not enough to test for correctness. Most of the problems happen while synchronizing signals with inputs/outputs and with other weird timing problems, glitches and unintuitive behavior that FPGAs provide (and the emulator behaves differently). I was using VHDL however. Anybody has experience with OpenCL on FPGAs to explain what difficulties persist (are the timing problems easier to solve)?

shriver 8y ago
There are a number of real issues with the emulation approach even now. Firstly, emulation isn't accurate - if you do floating point math in your application it will give you different results (within the tolerances of the OpenCL spec) on FPGA vs. CPU. So you can't test for correctness in the emulator. A second more serious issue is that getting performance that justifies using an FPGA requires tuning very carefully to the architecture. This may mean adopting pipeline architectures that destroy emulator performance (there's still issues with the emulator identifying that the design patterns for shift registers in FPGA look like pointer fun on CPU rather than mammoth memcpys). So for a huge part of the design stage the emulator is basically useless- because it tells you nothing about what you care about, since the performance of the emulator is often negatively correlated with performance on FPGA. This is made worse if you're doing hardcore FPGA tricks like mixed precision arithmetic. As you say though - the fact that timing is lost in the emulator also means you don't get a true idea of whether you have buffer overflows etc or lock-up. Adding debug into the actual design impacts the implementation on FPGA in a way that it doesn't for software - and is sometimes unintuitive.
- pjc50 8y ago
  > if you do floating point math in your application it will give you different results That seems like a gross weakness in the emulator; floating point isn't actually nondeterministic!
  - 8y ago

deleted 8y ago

[deleted]

rwmj 8y ago

I'm surprised he doesn't talk much about direct cost (rather than engineering cost). A decent FPGA developer kit will cost several thousands of US$, more expensive even than high end GPUs.

lightbyte 8y ago
You can buy this dev board to play around with and learn FPGA for $75, and it has extensive documentation and resources to help you https://www.sparkfun.com/products/11953 https://www.sparkfun.com/products/11953
- rwmj 8y ago
  But that's not a high performance FPGA. Believe me, I have a ton of FPGAs at home (starting even cheaper than that), and I write about them all the time: https://rwmj.wordpress.com/?s=fpga https://rwmj.wordpress.com/?s=fpga However if you're doing the sort of work which isn't just hobbyist stuff, you're going to spend 1000s on a board. This is the sort of thing commercial developers will be using: https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-...
  - lightbyte 8y ago
    If you're building a commercial product, a 3k dev board sounds incredibly cheap. My company spends orders of magnitudes more on licenses for an IDE extension (resharper).
    - rwmj 8y ago
      Absolutely. However I guess you'll also want to deploy your FPGA application at some point, which means buying FPGAs for all your servers too. So the cost is more analogous to the cost of a CPU/GPU than to the cost of an IDE/developer license.
  - FPGAhacker 8y ago
    You can get boards with a zynq 7020 on them for less than $200.

jaxtellerSoA 8y ago

Aren't FPGA's used mostly to test/design a circuit that you would then go on to actually fabricate/build? I could be wrong but I thought FPGA's were stateless (meaning if they powered off/reboot you loose everything and have to set it up from scratch again).

zwieback 8y ago
Yes and yes but new uses are emerging, it's like 3D printing: there's a crossover where the extra cost you pay for flexibility becomes too much to compete with hard wired logic despite the high initial cost.
- monocasa 8y ago
  To be fair, it's not new. People have been using FPGAs in that capacity for decades.
  - zwieback 8y ago
    Very true, but mostly EEs and embedded SW/FW engineers. I think the SW tools, although still awful, are reaching the point where more SW-focused developers can take advantage of FPGA flexibility. Which isn't to say every programmer shouldn't be forced to struggle through a Verilog or VHDL project - that'll put some hair on your chest and the fear of god into you. I'll see your async and raise you an "always @(posedge clk)"
stumpylog 8y ago
No, they retain state. We used an Altera DE1 in school and it retained our burnt in program until erased or reprogrammed
- zwieback 8y ago
  Probably burned into an external EEPROM or flash, the FPGA fabric itself still has to be configured by some external means. It's pretty fast but on-the-fly reprogramming of the FPGA logic is still an issue where you want to very quickly switch the logic on the FPGA.

amelius 8y ago

One reason could be to meet real-time constraints or to get predictable timing. This is becoming more and more difficult to do with modern CPUs for all sorts of reasons.

nastypasty 8y ago

Whats that for?

mladmon 8y ago

"...programming FPGAs is still an order of magnitude more difficult than programming instruction based systems." True statement. If you're offloading computation from a CPU, profile your application first, and determine if the FPGA board's architecture will allow you to improve performance. Don't underestimate the cost of communicating data to/from the FPGA/CPU.

petra 8y ago

I doubt that programming efficiency is what's holding back FPGA's for general compute. Why ? because we've seen decades of research in this area - so at least we have some tools(c for fpga isn't ideal, but still...), and a lot of the general mapping between what algorithms should be in FPGA. And Amazon FPGA's instance exist for over a year. So in that time, if there worth while services to offer with FPGA's, people would have offered them, or at least started. And sure programming complexity is a barrier. but entrepreneurs and VC's love competitive barriers. So where's all this VC funding going towards this area ? Where are all those startups ?

seliopou 8y ago
I disagree. FPGA design remains a highly-specialized area. Tools such as VivadoHLS, and other high-level synthesis tools, do provide some improvement in productivity though with inherent tradeoffs in design quality. There's been a lot of new hardware construction language popping up recently (e.g., HardCaml--which I happen to use, Chisel, Migen, PyMTL, etc.). They may bring something to the table in the coming years, but that's yet to be determined. HardCaml's pretty great though, IMHO. But then again I'm already biased towards OCaml, and I get to work with its creator!
amirhirsch 8y ago
Disagree. I worked in this space for 15 years and watched CUDA win a market for NVidia that was ripe for the picking by Xilinx or Altera. The culture around hardware design prototyping dominates the FPGA field and all attempts at making it approachable by software development are stunted by the proprietary ecosystem. I also think that high level synthesis is largely misguided since sequential imperative style isn't the correct way to think about FPGAs and also doesn't really address the lack of a good low-level language with an abstraction mechanism, and fundamental need for an operating system for running processes on a reconfigurable computing system.

Firerouge 8y ago

I've always thought FPGAs would be perfect to have hardware backed video decoding/encoding that could adapt to new codecs (like vp9) while also being updatable for new performance improving discoveries. It also seemed like it would go well with a generic radio subsystem, so you could compile hardware support for new wireless standards that come out after your hardware did (essentially an fpga sdr). It seems like there could be lots of uses for being able to on demand enable hardware acceleration for certain tasks a program might need lots of.

jakeinspace 8y ago
I spent this summer doing exactly that for an internship. I set up a xilinx Zynq chip to run a basic video capture and streaming program (based on gstreamer), with the encoding portion handled by the fpga. This chip has a baked-in encoder supporting AVC and HEVC, but I suppose you could implement or buy your own IP block for other codecs. Xilinx makes multiple boards based off the same chip with support for video codecs and SDR.
mirashii 8y ago
FPGAs are indeed commonly used for SDR as well. Ettus has a range of USRPs with FPGAs on-board, and you can find readily available IP cores for anything from Bluetooth to DVB-S.
- Firerouge 8y ago
  That's partially where I got my inspiration. Seems like it integrated properly it could be a great component in a general purpose PC to future proof it against changing needs and requirements
zymhan 8y ago
Experience seems to show that standardizing on a codec or instruction type is the most likely path. Apple iDevices have had hardware transcoding for video for a couple releases now. You really can't just have an FPGA that you recompile to a different architecture within a split second. They typically require compiling, downloading, and testing the the architecture you're deploying. Until someone comes up with a much faster to deploy FPGA, you'll likely not see enough efficiency gains in having a codec-specific processor given the time it takes to reconfigure the FPGA for each codec.

dojopico 8y ago

Another FPGA sweet spot is analyzing TB/PB-scale databases. Netezza programmed FPGAs to uncompress, project, restrict (including NULLs), enforce isolation & visibility and check CRCs at disk scan rates (>200MB/sec). When touching a handful of columns from a 20-200 column table, CPUs spend most of their time stalled on cache line misses. FPGA-projecting just those few columns into memory enormously increases cache hit rates.

paulsutter 8y ago
Plain C code can readily scan at a couple GB/sec on an ordinary Intel core, and NVME drives can transfer 8 or 16GB/sec

floatboth 8y ago

> An exception to the rule that GPUs require a host is the NVidia Jetson, but this is not a high-end GPU Well, the host is just on the same die, but it's still there

godber 8y ago

One interesting use case for FPGAs is where hardware qualification is very expensive, for instance for use in space. If a given FPGA is already space qualified, you just need to load new code onto it and you can skip the expensive qualification step for your new application. You can also consolidate functionality of multiple chips into that one qualified FPGA.

irq-1 8y ago
The expense for space is producing RAD Hard parts. (The designs are done on the same FPGA then a few RAD Hard chips are made.) https://en.wikipedia.org/wiki/Radiation_hardening https://en.wikipedia.org/wiki/Radiation_hardening

seliopou 8y ago

One clarification on the comment about latency. FPGAs are typically clocked much slower than a modern CPU. Typically, they run somewhere in the low 100's of MHz, whereas an Intel CPU clocks in at around 3GHz last time I went to the Apple Store. With a typical x86 multiply instruction having a latency of about, say, 3 cycles, putting that workload on an FPGA would result in a ~10x slow-down! The real benefit of an FPGA is that you get to decide what happens in any given cycle. So rather than being able to multiply two numbers in a single cycle like on x86, you could make your FPGA design do, say, 20 multiplications in a single cycle (space allowing). Which means that you can now multiply 20 numbers in 1/10th of the time it would take on x86. (In reality I think you have something like four execution units capable of perfoming parallel ALU operations per cycle, depending on the family.) So the latency benefit of an FPGA comes from flexible, almost (almost) unbounded potential for parallelism in a given cycle, not clock frequency. Hardware has to be designed to exploit this potential, otherwise it's not going to see any improvement in latency. Anyways, just something that is maybe obvious once you're told it, but isn't always mentioned in discussions like this. It certainly something that I didn't fully appreciate before getting involved in hardware design.

pensono 8y ago
FPGA latency is also much more predictable. Since you have cycle level control, you can know exactly how long any given operation will take. In a multi-threaded CPU, it's likely that the operation may be interrupted or delayed because of another process using the same resourt. It's also worth noting that FPGAs are often much closer to the I/O than a CPU on a motherboard. Pin to pin latencies are much reduced in a situation where direct access to I/O is available. An Ethernet stack can sit on the same silicon without having to serialize data between the CPU and the north bridge.
- 0xffff2 8y ago
  >In a multi-threaded CPU, it's likely that the operation may be interrupted or delayed because of another process using the same resourt. If you're considering an FPGA, isn't the alternative likely bare-metal CPU programming? In that case, you have just as much control over thread scheduling as you do over FPGA timing don't you?

ChuckMcM 8y ago

The author isn't aware apparently of over a decade of work done in FPGA/CPU integration. Both in more sequential languages like System C[1] or in extended instruction set computing like the Stretch[2]. Not to mention the Zynq[3] series where the CPU is right there next to the FPGA fabric. For "classic" CPUs (aka x86 cpus with a proprietary frontside bus and southbridge bus) it can be challenging to work an FPGA into the flow. But the problem was pretty clear in 2007 in this Altera whitepaper[4] where they postulate that not keeping up with Moore's law means you probably end up specializing the hardware for different workloads. The tricky bit on these systems is how much effort/time it takes to move data and context between the "main" CPU and the FPGA and then back again (Amdahl's law basically). When the cost of moving the data around is less than the scaling benefit of designing a circuit to do the specific computation, then adding an FPGA is a winning move. [1] https://www.xilinx.com/products/design-tools/vivado/prod-advantage/rtl-synthesize.html https://www.xilinx.com/products/design-tools/vivado/prod-adv... [2] http://www.stretchinc.com/index.php http://www.stretchinc.com/index.php [3] https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html https://www.xilinx.com/products/silicon-devices/soc/zynq-ult... [4] https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01029.pdf https://www.intel.com/content/dam/altera-www/global/en_US/pd...

blacksmythe 8y ago
>> The tricky bit on these systems is how much effort/time it takes >> to move data and context between the "main" CPU and the FPGA and then back again The sweet spot for FPGAs is when the data is streaming. You can build hardware where the data is passed from one stage to another, and doesn't go to RAM at all. Particularly where the data is coming in fast, but with low resolution (huge FPGA advantage for fixed point instead of floating point). FGPAs are much more efficient for signal processing from data collected from an A/D converter (e.g. software defined radio) or initial video processing from an image sensor.
- tomnipotent 8y ago
  > The sweet spot for FPGAs is when the data is streaming Netezza does this with their hardware, I've been dreaming of the day I could DIY and put a OSS RDBMS on top.

stevesimmons 8y ago

Does anyone have experience of Reconfigure.io [1] and their toolchain that transpiles Go for execution on FPGAs [2]? I am curious how it feels from the developer perspective, how it works in practice, and what types of applications it is a good fit for. [1] https://reconfigure.io https://reconfigure.io [2] http://docs.reconfigure.io/overview.html http://docs.reconfigure.io/overview.html

zackmorris 8y ago
I've waited 20 years for something like that, thanks for posting! FPGAs are great but I think the biggest problem with them is that they're an array of gates instead of logic units (like ALUs). So the learning curve to get to the point where you can place an array of cores and memories and have them all communicate is so high that most people never get that far. So that's been a huge barrier to exploring the problem spaces that GPUs are currently used for like AI and physics simulations. Hopefully using languages like Go/Elixer/Erlang/MATLAB/Octave etc will alleviate that to some degree. My gut feeling is that in 3-5 years we'll reach the limits of what SIMD can accomplish and we'll find it difficult to do the kinds of general-purpose MIMD computing needed to move beyond the basic building blocks of AI like neural nets and genetic algorithms. I stumbled onto these links a month and a half ago and I think something like this will make writing generalized/abstract highly parallelized code tractable again: http://aggregate.org/MOG/ http://aggregate.org/MOG/ https://en.wikipedia.org/wiki/Flynn%27s_taxonomy https://en.wikipedia.org/wiki/Flynn%27s_taxonomy Original at: https://news.ycombinator.com/item?id=17419917 https://news.ycombinator.com/item?id=17419917
monocasa 8y ago
It's so far outside the model of FPGAs, that I wouldn't even consider putting in the effort. It's like how regular code doesn't run well on the GPU, but much worse.
zymhan 8y ago
Unless you have optimized your code as much as possible to run on x86 or GPU and still find that you need a prohibitively expensive amount of processing power to accomplish the task, then and only then is an FPGA worth it. It is literally a DIY CPU architecture. So, unless you know exactly what it is about your current CPU's architecture that is holding you back, you won't be able to benefit from an FPGA-based design.

make3 8y ago

Is there a pipeline to compile tensorflow computation graphs to fpga? seems like this is one possible benefit of Tensorflow's fixed graphs, that they may be much easier to compile to fpga then other options Edit: Seems like some experimental work is being done with XLA (and llvm) https://www.google.ca/amp/s/www.nextplatform.com/2018/07/24/clearing-the-tensorflow-to-fpga-path/amp/ https://www.google.ca/amp/s/www.nextplatform.com/2018/07/24/...

foobaw 8y ago

What are some cool jobs for FPGA experts besides Intel and Military? It seems like there's not much availability.

kurtisc 8y ago
I recently spoke to someone at Broadcom who was moving networking processes from software to hardware using them, try looking into similar companies.
pkaye 8y ago
Lots of companies who design ASICs will prototype them on FPGA for catching bugs and start early firmware development.
kingosticks 8y ago
In the past I've seen job adverts for networking companies (routers) and hedge funds. Not sure if either of them count as cool.

neuromantik8086 8y ago

> The HPC community is already used to GPUs — getting people to switch from GPUs to FPGAs requires larger benefits. It's worth pointing out that some scientists haven't even made the leap to CPGPU computing yet and are still relying upon OpenMP / multithreading on general purpose CPUs, even when a GPU would be clearly superior. Anecdotally, I remember hearing that climate science simulations are particularly bad about taking advantage of new architectures for speedups, an assertion which possibly is supported by the fact that climateprediction.net simulations took several days using all 8 cores on my laptop to finish. Neuroimaging is also pretty bad, since other than Broccoli [0], most toolkits for preparing analyses don't leverage GPUs, even though I'd wager 80% of the steps involved image manipulations / linear algebra. [0] https://github.com/wanderine/BROCCOLI https://github.com/wanderine/BROCCOLI

cjhanks 8y ago
In my experience, it's true. And it's unlikely to change - the simulation code was largely written in FORTRAN and C over a period of 50 years. This is in fact what makes Intel Phi so appealing to some.
- amirhirsch 8y ago
  12 years ago I worked on High Level Synthesis at Xilinx converting atmospheric moisture simulations from FORTRAN...
- nl 8y ago
  For C/Fortran using LAPACK it should be as simple as relinking. https://www.olcf.ornl.gov/tutorials/gpu-accelerated-libraries/ https://www.olcf.ornl.gov/tutorials/gpu-accelerated-librarie...
fulafel 8y ago
I think these scientists are the real winners. Computers just work for them, they don't need to jump through hoops - eg, rewrite their software for immature proprietary software architectures. Chasing that last 10x of performance at great cost is for the desperate!
8y ago

saagarjha 8y ago

Is it just me, or does this article seem like it’s trying really hard to push Intel? For an article about FPGAs, failing to acknowledge the other (major) player in the market-there’s no mention of Xilinx anywhere in the article, while plenty of Intel/Altera-seems disingenuous. Really, the tone just seemed to stick out to me as an subtle advertisement piece; maybe it’s just me?

faragon 8y ago

I would love to see projects like MAME and MESS targeting FPGA hardware for near-perfect hardware emulation of classic hardware.

IvanGoneKrazy 8y ago
The Anologue Super Nt project uses an FPGA to run SNES cartridges unemulated. https://www.analogue.co/pages/super-nt/ https://www.analogue.co/pages/super-nt/
- faragon 8y ago
  But it is not Open Source. There are more commercial products using FPGA's for emulating gaming console hardware.

jwbensley 8y ago

"A couple of FPGAs in mid-air (probably)"

hyperpallium 8y ago

How long does it take to "program" a FPGA? i.e. compared with typing a command, and having it load into memory. What about a JIT that compiles hot code sections to FPGA? (Though compilation sounds too slow) EDIT "one or two seconds or at least 100's of milliseconds." https://electronics.stackexchange.com/questions/212069/how-long-to-program-a-fpga-seconds-microseconds-less https://electronics.stackexchange.com/questions/212069/how-l...

exabrial 8y ago

Why does the compilation take hours, is this an NP Hard problem?

mmirate 8y ago
If my memory of a Processor Design course is correct, arranging the desired functionality onto the finite resources of an actual FPGA chip, let alone in such a way as to get good performance (i.e. have critical paths be as short as possible), reduces to bin-packing.
- esfandia 8y ago
  The answer might be obvious, but I'm not a hardware guy: couldn't they use a FPGA to do the compilation itself, or at least the bin-packing part? Is there a way to code a general SAT-solver in FPGA?

tzs 8y ago

For those wanting to play around with an FPGA, this looks quite interesting: https://www.sparkfun.com/products/14829 https://www.sparkfun.com/products/14829 It's about half the price of the other FPGAs I've seen commonly used for hobbyist projects [1], doesn't need any separate programmer board to interface to your computer for programming, and has an open source tool chain available. I've not played with it, as it just showed up in a mailing from Sparkfun about new products. [1] such as https://www.sparkfun.com/products/11953 https://www.sparkfun.com/products/11953