5 ms·
Intel to Acquire eASIC: Lower Cost ASICs in FPGA Design Time
- slivym 8y agoThis is just bizarre - seems like corporate insanity to me. TO give some background to this, Intel's PSG is what Intel renamed Altera. Of course Altera was the FPGA company, and as part of their Stratix III/IV/V range they did 'HardCopy' which, basically was a structured ASIC! They canned it because in reality whilst customers want to be able to go ASIC in theory, it never really made much sense in practice. So what? They're buying a company that is doing something people don't want? That's what really worries me - because if the acquisition were going into the group that builds Xeons, basically as an enabling technology for an internal team that makes sense. But being part of PSG means that they're going to try and sell this to customers (again). For investors what you need to watch for is whether what they're really doing is buying growth. It's a classic move - buy small, similar companies and use get growth by upselling their product to your existing companies. But once all the customers have either bought or rejected you're back to brass tacks, the core business is missing growth/margin targets.
- amirhirsch 8y agoThey intend to integrate structured ASIC with EMIB in their server products. There is probably a path to hardened compute services with very rapid turn-around. I bet they can automatically determine which IP to harden based on the usage of their FPGAs.
- petra 8y agoThis technology will look very different once it is fully developed: on the latest process, using a much more ideal memory technology, enabling affordable single unit prototyping at the leading edge. Also, some of their patents ,not related to this tech, dealt with 3d fpga, a much more efficient form of fpga.
- andromeduck 8y agoLooks like that was 10 years ago though, might there be more viable applications now? I'm not entirely sure it's the same technology either but there doesn't seem to be much information on the matter.
- bgorman 8y agoIntel needs more customers for it's fabs.
- mtgx 8y agoIt can't even fab 10nm chips for its own business.
- voxadam 8y agoMost potential fab customers don't want or need 10 nm.
- picsao 8y agoUnless you are in the planned obsolescence by molecule current transportation buisness.
- nickpsecurity 8y agoThis 2017 survey supports your point: http://eecatalog.com/chipdesign/2017/11/26/semiconductor-ip-survey-2017-holds-surprises/ http://eecatalog.com/chipdesign/2017/11/26/semiconductor-ip-... Most are at 28nm-45nm with some at 55nm-65nm. The things they say they're concerned about also have some overlap with what eASIC's tech makes easier. That's on top of the number of companies that might be able to develop a FPGA but not full ASIC. eASIC's often a cheaper option for companies doing what's basically a bit faster and lower-power offering. So, there's definitely potential here for Intel. I hope they realize a good chunk of it. Who knows if they will.
- ksec 8y agoTrue, but in those case they are also much better served by TSMC rather then Intel.
- marcosdumay 8y agoA lot of things in the semiconductor industry changed since then. People don't have the expectation that general purpose designs will improve an break their specialized companies anymore. The market for SoC is absolutely huge now, and it may be worth getting into it even if it's to get a small share. There are very large clients now that may think it's worth designing chips for internal use.
- duxup 8y agoI worked for a company who bought a smaller company to get into X business. They handled the engineering teams terribly, everyone quit, product sucked, company moved on. Three years later we bought what was basically the same company but handled everything carefully and off the product went. Could be as simple as they want to take a second swing at something that they thought wasn't worth it earlier....
- kevin_thibedeau 8y agoHaving them in the same group means that the Altera and eASIC tooling devs can work together more closely.
- tw04 8y ago>But once all the customers have either bought or rejected you're back to brass tacks, the core business is missing growth/margin targets. What exactly is your suggestion at their market penetration? They can't manufacture more demand for CPUs out of thin air. The logical next step is exactly what they're doing - find complimentary products to sell into your existing installed base.
- pooya13 8y agoArticle mentions that eASIC replaces SRAM based routing with a scheme that uses via. What is "via"?
- detaro 8y agohttps://en.wikipedia.org/wiki/Via_(electronics)#In_IC https://en.wikipedia.org/wiki/Via_(electronics)#In_IC Connection between layers in a chip. Presumably they have everything in the chip standardized except one/a few layers, where vias are added to connect parts per customer specification.
- amirhirsch 8y agoSRAM routing (in FPGA) uses volatile storage to switch programmable interconnect points. Via routing implies that their structured ASIC has a fixed routing network that only requires one mask layer to connect routes resulting in much higher density connectivity than SRAM schemes in FPGA. Via layers tend to have simpler masks than other layers too.
- deleted 8y ago[deleted]
- brandmeyer 8y agoIf you read up on the structure of an FPGA lookup table (LUT) in detail, you'll see that most of their size is taken up as memory. A Xilinx 7-series LUT6 Configurable Logic Block (CLB) is a 64-entry 1-bit sram, read out with a 6-bit address. If you don't need the ability to reconfigure the system any more, you can hardwire each of those 64 entries to the VDD and VSS rails instead. Its not nearly as efficient as the circuits you can get with a set of dedicated logic cells, but its much more efficient than the baseline FPGA fabric. If the customer has already validated their logic on FPGA fabric, then its also much cheaper. You just ask these guys to "burn" it into an ASIC and you suddenly get a few hundred extra MHz. Why are they called 'vias'? Because ASIC layout is somewhat similar to PCB layout - transistors go on one layer, and there are a dozen or so layers of routing wires below them, with vias in between the layers. So you can replace the transistors that would have been implementing SRAM cells for read/write LUTs with vias to power/ground layers instead.
- baybal2 8y agoImagine a CPLD that is hardwired.
- ksec 8y agoMcAFee, Infineon, Havok, ZiiLabs ( Or previously more widely known as 3Dlabs ), Altera, Recon Instruments, Mobileye. Or Name me one thing good that Intel has ever done with their Acquisition. There is something seriously wrong with Intel.