5 ms·
Big Trouble at 3nm
- deepnotderp 8y agoTL;DR: FinFETs are running out of steam without a powerful "scaling booster"* so GAA-FETs ?, wires suck and continue to suck and development costs are going up so let's misrepresent that and use ridiculous numbers for it. *Debatable: https://ieeexplore.ieee.org/document/7890390/ https://ieeexplore.ieee.org/document/7890390/
- Xcelerate 8y ago3 nm is nuts. I used to perform molecular dynamics simulations in boxes that were 10 nm on each side. You can count the atoms lined up within 3 nm of space.
- 6nf 8y ago3 nanometers equals about 6 silicon atoms in a crystal lattice!
- ianai 8y agoMy gut instinct from reading about quantum computation is that we need a new paradigm, or several. Maybe it makes less sense to be trying to do binary logic at that scale, for instance. Or maybe we should be engineering at a quasiparticle level.
- imtringued 8y agoNothing about 3nm is 3nm.
- Taek 8y agoThe actual gate pitch of a 7nm process is 54nm, and the interconnect pitch is 40nm. Though the name is "7nm", it's far from it.
- daveguy 8y agoThe way I (not EE) understand it the size of a process considers just one dimension. So transistors can be tightly packed along that axis and less tightly packed along the other axis of a wafer. Have the gate pitch / interconnect in the range of 40-54nm hit a more difficult limit than the 7nm aspect? It seems like there is significant space for improvement in those dimensions where you could still double density. Should process nodes be referred to as 7nm x 54nm where new generations drop gate pitch too? Is there something inherent to the process that fixes the other dimensions when you have a "7nm" node for that particular metric?
- ianai 8y agoI’m not entirely sure you and OP are talking about the same things. But you both probably knew that.
- tsenkov 8y agoWhere does the increase in Software expenses for IC Design stem from? https://semiengineering.com/wp-content/uploads/2018/06/nano3.png https://semiengineering.com/wp-content/uploads/2018/06/nano3...
- abainbridge 8y agoGood question. That's a strange graph in general. I think most items have little to do with the node choice. From the article: > The $1.5 billion figure involves a complex GPU at Nvidia I think the graph shows how much it costs a company in total to design a chip at different nodes. In general, chip vendors add more functionality with each generation. That seems to be what the graph shows. The article says the graph comes from International Business Strategies. Their web page tells me to install Flash, which was enough to prevent me looking further: http://www.ibs-inc.net/#!reports http://www.ibs-inc.net/#!reports Also, someone should tell them that IBS stands for Irritable Bowel Syndrome.
- flyinglizard 8y agoThat probably reflects the higher complexity of ICs at cutting edge nodes - being that newer node are an enabler for denser ICs.
- pjc50 8y agoNot clear, but I suspect it means newer, better modelling and synthesis.
- rys 8y agoThere isn’t that kind of increase at all, it’s pure BS. Costs for semiconductor design don’t scale that way. Even the costs for semiconductor manufacture aren’t like that.
- mamon 8y agoIt seems that Intel already is in the Big Trouble at 10nm, so 3nm seems even more unrealistic goal.
- theshadowknows 8y agoIs decreasing the spacing of gates and increasing the density of chips the only way to squeeze more performance out of chips?
- ecarrick 8y agoNot necessarily. Parallelization has allowed better performance from chips. Adding more cores has allowed better throughput but the benefits are seen more on the application side. They could make the chips bugger, but the problem with expanding outward is the routes connecting the transistors become too long and suffer increased time delay due the increased resistance of the long line. Without being able to make chips larger the only way to get better physical performance is to increase density.
- marcosdumay 8y agoIt's not just decreasing spacing. It's decreasing wire resistance and gate capacitance. That's what makes the most difference. It is also about making things cheaper, because your costs are constant for a wafer, but the use is measured by gate count. That said, things are not that simple for a long time already.
- deepnotderp 8y agoWire and contact resistance has been steadily increasing and FinFETs actually increased gate capacitance.
- marcosdumay 8y agoAs I said, things have not been that simple for a time.
- no_identd 8y agoWell we could switch everything to balanced ternary (which has a higher radix economy not just than binary, but also than unsigned ternary. Something most people talking about ternary neglect to mention - because the traditional formula for calculating radix economy isn't generalized.), but that comes with a heap of other (tractable!) problems...