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Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors
- mr__y 8y agoInsert some random Moore's law comment here
- auvi 8y ago"Price: Arm, Leg" ... hard to miss the sarcasm.
- jayonsoftware 8y agoArria 10 FPGA is kind of mid range, I think they go around for 500 bucks , you can buy the dev board for 5K (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html https://www.altera.com/products/boards_and_kits/dev-kits/alt...)
- denkmoon 8y agoWhy are dev boards that much more expensive in general? I can't believe that it costs 10x as much to "just" put the chip on a pcie board.
- userbinator 8y agoI believe it's a technique for filtering out everyone but "serious" customers, because whoever buys one and tries to make it work is inevitably going to ask questions about it.
- dbuder 8y agoTo stop it becoming a retail item and to fund the software dev.
- brandmeyer 8y agoThese are usually full-custom boards, very low-volume, with many layers and fine pitch traces. The parts themselves may have thousands of pins, routed across a dozen layers or more. So the non-recurring engineering (NRE) costs are very high, and you don't get to recover them over much volume. Even at 10x the cost, the vendor is still losing money.
- agumonkey 8y agofunnily it also applies down the chain, even dollar ESP chips dev boards are 10x the cost of the bare pcb :)
- sannee 8y agoIf you are seriously interested in using 500$ chip in any "interesting" volume, shelling out 5k$ for a dev board is nothing you would care about.
- bsder 8y agoUm, the FPGA chip on that board retails for $10K according to findchips.com so ... (of course, anyone really ordering these class of chips is going to order them directly from Intel or Xilinx--but that doesn't mean the FPGA will be cheap) Intel isn't making a lot of money on those boards if they aren't actually taking a loss. 1) A PCI-e board is non-trivial. It requires some engineer to sit down and do some serious signal integrity work. 2) A board with a fine-pitch BGA is non-trivial. These boards generally have via-in-pad and blind vias on the top two layers. The boards are also generally 8-12 layers. 3) The support circuitry on those boards in non-trivial. There's high-speed, fine pitch connectors that are probably in the $100 each range, themselves. 4) Really, you're paying for customer support. You will hit bugs. You will have to communicate with Intel. You probably won't order enough volume to make it worthwhile for Intel.
- simias 8y agoI have an Arria 10 SoC dev board (not the PCI one, the stand alone version). It's a very complex and fully featured board, it's just not just a "breakout board" for the FPGA. It's also clearly aimed at companies looking to integrate an Arria 10 into their designs, not hobbyists looking for a cheap FPGA board and the pricing reflects that.
- kev009 8y agoOne stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that reality, and their product development arm seems too taxed to bridge the gap.
- sannee 8y ago> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?
- analognoise 8y agoWe get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.
- akhilcacharya 8y agoHow do you define "bank"?
- jayonsoftware 8y agoIf anyone is interested in using C# on a FPGA to learn take a look at https://hastlayer.com/project https://hastlayer.com/project
- monocasa 8y agoWow, someone managed to make something even worse than the "compile your C to an FPGA" tools you see occasionally. The model is just too different for these things to make sense 99% of the time. It's like trying to run general purpose code on a GPU, but even worse.
- __jal 8y agoWhy would anyone in their right mind try (or even want to try, except as a lark) this? "...The input of Hastlayer can be a program written in dozens of programming languages (including several of the most popular ones as C#, C++, Python, PHP..."
- londons_explore 8y agoFor those of you missing context to understand why it's a bad idea... Typical programming languages run code one line at a time from the top to the bottom, occasionally calling functions or looping. FPGA's instead have code which specifies a kind of circuit diagram of what is connected to what. You can make something to translate one to the other, but by translating a programming language to a circuit diagram you usually end up bits of creating circuitry for each line of code, and then extra circuitry which makes each bit be activated in sequence. That typically leaves 99.9% of the circuitry unused (deactivated) at any point in time. FPGA's don't have much space for circuitry, so by translating a program from C to an FPGA directly you'll usually end up with a huge design with a very low throughput, since the vast majority of the circuit is sitting idle most of the time. Real FPGA designs will typically aim to use circuitry very sparingly, and keep as much of it in use as possible all the time to get maximal performance. Complex, sequential and non-performance critical tasks are typically not a good fit for an FPGA and are usually offloaded to a programmable processor instead.
- 8y ago
- ksec 8y agoI wonder if amd could produce epyc with tsmc and xilinx. xilinx is a much better choice in fpga
- hoodoof 8y agoWhat's the use case of an integrated FPGA?
- vegetablepotpie 8y agoI can think of two possibilities: 1. Hardware accelerated custom crypto algorithms. 2. Specialized co-processor. You could implement an exotic processing architecture on the FPGA to off-load computations to, like a complex number processor with 52-bit words in a custom floating point format for a specific application.
- agumonkey 8y agoI don't know how fast the FPGA can reconfigure itself or part of it, but you could also have per process bare metal JIT
- slivym 8y agoIt takes in the order of seconds to reconfigure. JIT is not really viable.
- GuB-42 8y agoAnother use case is if you have a large amount of asynchronous I/O and real time constraints.
- 1024core 8y agoSo what can you do with 1.15M logic gates that are in that FPGA? Can you, say, multiply, say 2 256x256 FP32 matrices?
- sidhu1f 8y agoTop of the line Arria-10 FPGAs have about 1500 floating point MACs [1]. Using such a device, Intel claims ~1 TFLOP sustained for GEMM, the standard matrix multiply operation [2]. [1] https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/pt/arria-10-product-table.pdf https://www.altera.com/content/dam/altera-www/global/en_US/p... [2] https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01267-fpgas-enable-high-performance-floating-point.pdf https://www.altera.com/content/dam/altera-www/global/en_US/p...
- slivym 8y agoI would give a very strong health warning about taking those numbers seriously. What that 2nd reference doesn't make clear is that it is NOT a standard Matrix Multiply Operation, it's an 11 row by 16 column Matrix Multiplication. This is important because unlike in software where performance scales well. For FPGA you would have to decompose every matrix multiplication into 11x16 style matrix multiplies. They don't mention this overhead in their specs.
- igravious 8y agoFive top comments in and you're the first to ask the this question. Given how exotic this piece of silicon is I'd love to know too. This is the Intel webpage I found[0]. From there there's a link to an Altera page[1]. This is the marketing blurb that Anandtech got some of there info from[2]. A number of obvious interesting applications jump out at me: crypto acceleration for mining, machine learning acceleration, JIT acceleration for interpreted languages… How doable is all this? Would you have to roll your own code or are there libraries? Wrt interpreted languages, I use Ruby fairly often and now that there's MRuby[3] I wonder if Ruby could be made run blazingly fast on something like this Xeon+FPGA thing? Oh to have a spare $€£￥ to get me one of these. [0] https://www.intel.com/content/www/us/en/servers/accelerators/accelerators.html https://www.intel.com/content/www/us/en/servers/accelerators... [1] https://www.altera.com/solutions/acceleration-hub/acceleration-stack.html?_ga=2.21313979.1890327809.1526633423-1729697991.1521483926 https://www.altera.com/solutions/acceleration-hub/accelerati... [2] https://itpeernetwork.intel.com/intel-processors-fpga-better-together/ https://itpeernetwork.intel.com/intel-processors-fpga-better... [3] https://github.com/mruby/mruby https://github.com/mruby/mruby
- ajdlinux 8y ago> Also in the announcement was a mention of Intel’s desire to offer a discrete FPGA solution with a faster high-bandwidth coherent connection, although details of this interconnect were not provided Sounds a lot like what OpenCAPI (https://opencapi.org https://opencapi.org) offers. (disclosure: work for IBM on CAPI/OpenCAPI firmware enablement)
- slivym 8y agoWhat I'm really interested to know is how this looks from a power-performance perspective. An Arria 10 can draw 20-40 watts (I'm not sure that 90w is really realistic), and the TDP for the Xeon is 165W. When I saw the discussion about this in the past with people who work at Intel the discussion wasn't 165+90 = 225TDP. It was actually "Oh so you want to use the FPGA, better turn off 6 of those Xeon cores! That could be a real problem for getting performance out of these systems.
- virtuallynathan 8y agoIntel Scalable CPUs are already at 205W TDP, and also see: https://en.wikichip.org/wiki/intel/xeon_platinum/8124 https://en.wikichip.org/wiki/intel/xeon_platinum/8124
- qubex 8y agoI remember Faggin (of microprocessor fame) dabbling with the idea of creating an all-FPGA ’hypercomputer’ back in the late 1990s, and even going as far as launching a start-up called Starbridge Systems. Nothing much came of it then, but here’s a WIRED period piece with all the de rigeur gushing optimism of the era. https://www.wired.com/1999/02/the-super-duper-hypercomputer/ https://www.wired.com/1999/02/the-super-duper-hypercomputer/