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6th RISC-V Workshop Proceedings
- pulse7 9y agoFolks, you must watch this: https://www.youtube.com/watch?v=1FtEGIp3a_M https://www.youtube.com/watch?v=1FtEGIp3a_M
- kobeya 9y agoWhy?
- pulse7 9y ago"50 years of Computer Architecture in about 15 minutes" + current state and future
- MycroftJones 9y agoWow, that video is a lecture by one of the leaders of RISC-V. I had no idea there was a RISC-2 and RISC-3, and that they were optimized for SmallTalk and Lisp respectively. Wonder what Alan Kay has to say about RISC-V? He's been banging on about how Intel messed up their chip design, does he approve of RISC-V? Seems like the perfect time to get things done right.
- IshKebab 9y agoThat was no-way near 15 minutes. Great talk though.
- kdeldycke 9y agoTIL, IBM 360 is the reason why bytes are 8-bits long. See: https://youtu.be/1FtEGIp3a_M?t=1m49s https://youtu.be/1FtEGIp3a_M?t=1m49s
- musha68k 9y agoGreat presentation, thanks for sharing!
- nl 9y agoThe NVidia slidedeck is pretty interesting: https://riscv.org/wp-content/uploads/2017/05/Tue1345pm-NVIDIA-Sijstermans.pdf https://riscv.org/wp-content/uploads/2017/05/Tue1345pm-NVIDI...
- jacquesm 9y agoIt is actually. Lots of interesting tidbits. Also this, which I completely missed: http://www.cnbc.com/2016/09/20/chinese-company-hacks-tesla-car-remotely.html http://www.cnbc.com/2016/09/20/chinese-company-hacks-tesla-c...
- akavel 9y agoanyone knows what does the "TCM" mean in the slide "Why RISC-V for Falcon Next"?
- CodesInChaos 9y agoProbably tightly-coupled memory http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0198e/ch05s02s03.html http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....
- CalChris 9y agoWhy is an extensible ISA a requirement for a controller chip?
- legulere 9y agoSo I guess the thing currently keeping RISC-V from moving forward is ratification of the privileged spec, which is planned for end of 2017/2018? https://riscv.org/wp-content/uploads/2017/05/Tue1115-Technical-Committee-Update.pdf https://riscv.org/wp-content/uploads/2017/05/Tue1115-Technic...
- majewsky 9y agoI don't follow RISC-V development closely, so please define "moving forward". What are the steps you want to see taken?
- legulere 9y agoProduction of chips that support the privileged specification, which is needed for operating systems like Linux to run. So far there is only one microcontroller chip being produced.
- razer6 9y agoNot exactly true. There exist different tapeouts in academia (e.g. http://asic.ethz.ch/2016/Patronus.html http://asic.ethz.ch/2016/Patronus.html or http://asic.ethz.ch/2015/Imperio.html http://asic.ethz.ch/2015/Imperio.html) as well as in industry (which are not public).
- lloydjatkinson 9y ago> privileged spec I hope this refers to ring-0-like instructions such as x86 STI, and not some kind of OEM/manufacturer "you can only use this set of instructions if you pay us" type privilege?
- fnord123 9y agoYes, indeed it is about ring-0, hypervisor type stuff. https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf https://github.com/riscv/riscv-isa-manual/blob/master/releas...
- MycroftJones 9y agoSo, how does RISC-V compare with Donald Knuth's MMIX instruction set? Did they use it as a starting base? Consider it at all? Be cool to program MMIX in actual hardware.
- zzo38computer 9y agoI happen to like MMIX, although I think is good they can make these free instruction set such as RISC-V and MMIX.
- renox 9y agoWhat makes you think both are related? AFAIK MMIX isn't a very "practical" ISA.
- FullyFunctional 9y agoIf you consider an FPGA board real hardware, then yes, I've run MMIX programs, including graphics, on real hardware: https://github.com/tommythorn/fpgammix https://github.com/tommythorn/fpgammix Caveats: this is some of the worst Verilog I've even written; I was explicitly racing ahead learning about MMIX as I went along. In the end I had a large subset (integer usermode) when I abandoned it. As much as I wanted to like it, it's really a pretty terrible architecture from most perspectives: it's impossible to scale down, hard to scale up, and nearly impossible to generate good code for. In contrast, RISC-V is IMO the nicest RISC ISA ever design.
- CodesInChaos 9y agoOne thing that worries me about RISC-V is how much encoding space for (major) opcodes they already used up. There are 7 bits to encode the opcodes. Of those 128 possible values, 3/4 are used for 16-bit compressed/thumb instructions. The remaining 32 values are allocated as follows: * 4 are for custom instructions * 4 are for larger than 32-bit instructions * 21 are already used * 3 are reserved for future use While there is some space for minor opcodes (encoded via func3/func7) inside of the already allocated major opcodes, this allocation seems overly generous to me considering how young the instruction set still is. I would have felt far more comfortable with compressed instructions only taking 1/2 instead of 3/4 of the total available space.
- rwmj 9y agoRISC-V isn't limited to 32 bit instructions. In fact RISC-V insns are variable length, and as well as 16 bit (compressed extension) they can be longer than 32 bits -- in fact much much longer. More details in section 1.2 of this document: https://riscv.org/wp-content/plugins/pdf-viewer/stable/web/viewer.html?file=https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf https://riscv.org/wp-content/plugins/pdf-viewer/stable/web/v...
- PedroBatista 9y agoAt the end of the day, RISC-V will only succeed if I can buy a board where I can attach some SATA drive, a monitor and keyboard/mouse the same way people buy some ITX board. This might be tough to hear for people discussing the ins and outs of RISC-V and why is so much better than x86 or ARM and the big name sponsors don't make it any better with the usual tight hugs and lullabies. But you need to put it in the hands of the people just like "the PC", otherwise it will be a pet project waiting to be forgotten by everybody other than the nostalgic ones.
- abelsson 9y agoThere's gazillions of embedded processor cores in every device you own. Your SSD, network card, phone, motherboard, router, TV, modem, car, fridge, you name it all have multiple processor cores running some piece of firmware you never see. RISC-V has a pretty good value proposition for those: an open standard with no licensing costs with a rapidly maturing software ecosystem. To say that RISC-V will only succeed if you can attach a monitor to it only betrays a very narrow view of where processors are actually used.
- pjc50 9y ago... most of whom are already using ARM. Intel - Intel - tried to compete in the embedded market and has recently quietly withdrawn several of its products. It's a tougher market than it sounds, and it's also more conservative than you'd expect.
- nickpsecurity 9y agoIs that because it's that hard or they bet against ARM with its style of ecosystem?
- pjc50 9y agoI think a combination of things, really. They never scaled down properly to really low end devices. The Intel systems had poor peripherals for some reason with high latency. They didn't really grasp the detail of what was needed for either the "maker" or industrial markets. And of course it wasn't a licensable IP.
- inetknght 9y agoWhat RISC-V needs for high adoption, is a well-marketed product similar to the Raspberry Pi. Give me an open source model board with a kernel, network, graphics, peripherals, and general-purpose I/O. Give it to me cheap. Give it to me with a desktop environment. Give me example simple real-world use cases ("build a ping response box!", "build a home video recorder!", "build an internet-enabled light switch!", "build a sound amp!", "build a robot to take over the world!", etc) and the hardware and software for a DIY-er to... do it by themselves. Give people hardware, software, and examples (monkey see, monkey do), and you'll find more people adopting RISC-V.
- ajross 9y agoThat's a big ask. Right now RISC-V has a handful of open source CPU cores. There's no open source network, graphics, peripheral and GPIO hardware that can be cheaply plugged into a synthesized design that can be sold at the price you want. Which is to say, while there's plenty of stuff out there that someone made work on a FPGA once, there's nothing with a track record and validation/driver stack ready that you can throw into your tools and expect to get a working chip with. And that's what those SoCs you find in the Pi and similar boards need if you want to get them out at the small-integer-dollars price point: no-brainer existing IP that won't surprise anyone along the manufacturing and support chain.
- rjsw 9y agoThere are simple open source cores for quite a few IO standards. Some ARM SoCs use Cadence or Synopsys cores. What could be a good advert for RISC-V would be to design a SoC that used a full featured RV64 main core and simpler RV32I cores as offload engines for each IO device.
- tyingq 9y agoThe lowrisc project has something like that. They call them minion cores. http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-minion-cores/ http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-...
- 9y ago
- throwaway000002 9y agoI used to be a big champion of RISC-V, just look at my submission history, but I've become increasingly weary due to SiFive's dubious leadership. 1) It's still impossible for anyone to get their hands on an FE310 chip over half-a-year on from the release of the HiFive board. 2) They promised open-source cores, but somehow backtracked due to "customer requests". How does this make any sense? And if so, just have an open-source version, and a closed-source one that, I dunno, has a SiFive logo on the mask. I was really inspired by them, now I'm mostly dejected. Still, I'm hoping someone like ST takes their peripherals and makes an MCU with a RISC-V.
- jackckang 9y agoSorry to hear that you're feeling dejected. On your questions: 1) We are providing FE310 samples to folks who ask us for them at info@sifive.com See our past forum posts for similar requests: https://forums.sifive.com/t/assistance-getting-in-contact-with-sifive/562/6 https://forums.sifive.com/t/assistance-getting-in-contact-wi... https://forums.sifive.com/t/e300-on-the-market-other-sbc-s-with-it/421 https://forums.sifive.com/t/e300-on-the-market-other-sbc-s-w... 2) We do provide both versions, just as you recommended. SiFive continues to maintain the Rocket repository at https://github.com/freechipsproject/rocket-chip https://github.com/freechipsproject/rocket-chip We intend to continue to maintain this core and ensure it's compatible with any updates to the RISC-V specification. For commercial customers who do not want to utilize rocket-chip, we are providing them with other options. -Jack (from SiFive)
- throwaway000002 9y agoThanks Jack for taking the time to respond. Keeping the faith alive...
- childintime 9y agoWhat's needed, and possible, today, is a competitive and relatively simple AVR or ARM-M0/M3/M4 replacement (with I2S). Such a chip is likely to receive stellar support from the maker-community. My gut feeling says that such a chip is likely to come from Samsung, but NXP and Expressif are also likely candidates. All are RISC-V members. Anything more complex should wait until the specs are complete.