14 ms·

Open Source Needs FPGAs; FPGAs Need an On-Ramp

309 points by heathjohns 10y ago

pryelluw 10y ago
Are there any fpga open hardware implementations available?
- mlaretallack 10y ago
  If you mean stuff that can run on FPGA's then https://opencores.org/ https://opencores.org/
  - pryelluw 10y ago
    I also mean the actual hardware. :)
    - monocasa 10y ago
      This is the only project I know of. http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/
    - rvense 10y ago
      Quite sure the answer is no. There was a student project a while ago but it was more of a proof of concept. Open source chips of any kind are few and far between, and generally not at the cutting edge, technology-wise. Patents, as usual, will make this hard, before we even get to the economic aspects.
      - analognoise 10y ago
        I'd be more than happy with 1997-era (20 year patent expiry) FPGAs if they were open. Unfortunately, I don't think anyone else would.
        rvense 10y ago
        Me too. For some things you need to be as fast or cheap or low-power or whatever as the competition to win, other times you just want to see how far you can go. At my hackerspace we've been mucking about with Clifford Wolf's PicoRV Risc-V implementation on Lattice Ice40 FPGAs lately. This'll give you something that's maybe on par with a lower-end ARM Cortex-M, plus the flexibility of the few thousand spare look-up tables. All open and hackable with open source tools (except for the actual FPGAs, mind). It's not much, but it's a start.
- lvoudour 10y ago
  None that I'm aware of. It would be a great leap as it would open the way for open source tools that go beyond netlist generation, but right now all major vendors keep their architecture proprietary and you need their tools to program their FPGAs
- buildbot 10y ago
  Actual chips, not as far as I know. There is a completely open source tool chain for a small FPGA, the icestorm project. The VPR project by university of Toronto has several architechure models defined, but there is probably no way to turn these into a real chip. FPGa vendors in general are extremely secretive about their designs. (I'm a grad student working in The FPGA space)
  - zafka 10y ago
    > FPGa vendors in general are extremely secretive about their designs. That is the part that saddens me. I had always wanted to be able to play with the internal programming. Back when I started they were not anywhere as big, and we almost had visibility.
    - buildbot 10y ago
      At least with VPR you can define /modify your own FPGA architecture file! They are written in xml and parsed by the tool when doing place and route.
vvanders 10y ago
Something that's not really spoken to but is just as important is that FPGA development isn't software development. You're specifying hardware and usually that hardware doesn't just scale to new platforms. Time will tell if Open Source can make the transition over to that domain I'm cautiously optimistic but I think there's a larger cultural divide there than called out.
- pryelluw 10y ago
  Maybe we could have a hardware interface designed to be open?
  - Sanddancer 10y ago
    For inter-IC interfaces, AMBA [1] and Wishbone [2] are open standards for connecting various sections of a chip --bridge between cpu, i/o bits, etc. External interfaces are also pretty open. A lot of FPGAs have dedicated logic for talking with a PCI bus, I2C bus, etc. Unless you're doing something extremely interesting and specialized, hardware's pretty open as is. [1] https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_A... [2] https://en.wikipedia.org/wiki/Wishbone_(computer_bus) https://en.wikipedia.org/wiki/Wishbone_(computer_bus)
- pdelbarba 10y ago
  It can and it can't. It's sort of like microcontroller code. You can define a core set of functions (like an FFT or something) that is very portable, but the peripheral mapping (which pins to output on, where resources are located, etc) is chip specific.
  - vvanders 10y ago
    Yeah, even things like Block RAM, DSP units, carry + routing and other parts vary widely from chip/vendor.
- blackguardx 10y ago
  FPGAs are sexy to many people because they are exotic. Imagine a custom chip designed to do whatever you want and able to be reconfigured on the fly? The problem is that many aspiring learners want to approach it like a software problem. That can be a valid approach as long as they are willing to learn new abstractions. Many are not and then get frustrated and blame the tool ecosystem. Granted, the tool ecosystem does suck, but people (like me and others) are doing real work with these tools. Even if you scoff at FPGA tool quality, you have to remember that almost every ASIC out there was developed with similar (maybe slightly better) quality tools. There has to be flexibility on all sides. Tool vendors have to adapt to changing times (more open ecosystems) and software developers branching out into FPGAs have to be willing to learn how hardware works.
salesguy222 10y ago
Do FPGAs have a future beyond "prototyping non-memory intensive algorithms for eventual ASIC implementation"? It seems to me that the scale out + scale up method of x86 and GPUs are the most promising and profitable arenas still, besides some very niche and very particular applications? I could and would like to be wrong. I'd go learn FPGA dev then if there were things that needed accelerating and were personally lucrative to me :)
- syntheticnature 10y ago
  Sometimes they're good for "need ASIC-like results in a low-volume design" but that's more a special case of what you give, and of course the 'upgradable glue logic' case also is in play. I think the killer application would be to have programatically reconfigurable FPGAs that reconfigure on the fly to fit the needs, which has been discussed in various overhyped ways in the past, but I don't think the tooling is there. This effort might or might not make that possible -- imagine a chip where, say, the regex you're going to use to scan 1GB of data could be turned into an FPGA and then it just shovels the whole thing through a "HW" FIFO that detects matches much faster than a processor could. Nifty... but is it worth the effort to do?
  - pdelbarba 10y ago
    You can kind of do this now if you want. The SOCs like the Cyclone V or Zinq have an arm core or two surrounded by FPGA fabric. The only barrier right now would be the dynamic reloading of the FPGA which I haven't seen done, but would be simple in principle (as opposed to having a soft core that would likely have it's state interrupted if you re-flashed everything)
    - aseipp 10y ago
      Most newer Intel (Cyclone and beyond) and Xilinx (-7 series) support various levels of partial logic reconfiguration. If you plan your device layout right, you can simply reprogram a region of fabric that is hardwired wired to the 'shell' of your system (which is connected to the peripherials). If you have setups like Vivado's SDSoC/high-level synthesis, you can do things like dynamically reconfigure OpenCL kernels, etc. Of course, the problem is synthesis, verification, testing etc is all rather difficult in practice and takes a long time. The boards themselves also can't do synthesis/compilation, obviously, since they're fairly limited and it's a time-consuming process. You'd have to make it act more like an OTA update system, but that comes with a lot of its own problems...
zafka 10y ago
I love FPGAs in a simplistic sort of way. I first started working with them when I was in school (1994-96) and thought I was going to spend my life with them. Other than some simulations with very expensive software that had been donated by Motorola I never actually used FPGAs. But from when I first started looking at them, I thought they would be the building blocks for an AI machine that could be added on to forever. I still think so, but I thought that there would be more visibility into the internal workings of the chips.
PhaseLockk 10y ago
I'm not exactly clear on what the post is advocating. If it's saying that there should be an open source implementation of an FPGA, then I just have to say that I think there's no way that's happening anytime soon. There are way too many hurdles. If the argument is just that the open source community should leverage FPGAs more as a means of creating more powerful "open source" hardware, and that there should be more resources for people to learn how to write hardware, then I guess I agree with that. But I don't think FPGAs will be the panacea the author seems to think they will. FPGA implementations will always entail a performance and/or efficiency hit compared to ASIC implementations, and I think many people won't want to take that hit, limiting the number of users who are willing to adopt the open source solutions.
- heathjohns 10y ago
  Author here - I'm advocating the latter. I agree with you to a point. However, I believe that those things that have been with us for decades: sound cards, 2D graphics adaptors, network cards, etc. can be done in FPGAs, and should be. The speed is there, and the power used by the southbridge and peripherals is eclipsed by the processor and the screen backlight, so I don't think the power consumption is worth worrying about (I'd be interested to see evidence to the contrary, though). Put another way: much of the foundational chips on motherboard are no long performance-sensitive, so we shouldn't be paying a compatibility price for it.
  - petra 10y ago
    Why not just choose a small set of "golden" chips, create high quality drivers that abstract away incompatibilities if possible, and verify the heck out of that ?
    - heathjohns 10y ago
      The trouble with "golden" chips is a) the manufacturer can EOL it at any time (and I don't think just the OSS people are numerous enough to keep any specific set in production), and b) it freezes things in time. For things that don't change much (e.g. sound cards), no problem, but there's still improvements to be made in other areas. The focus for FPGAs has traditionally been performance, but I think there's a model where they can be used for both long-lived compatibility and cutting-edge devices living together on the same chip.
nickpsecurity 10y ago
The trick is getting more EE's to spend their grants on open-source FPGA's and tooling: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.html https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-... http://opencircuitdesign.com/qflow/welcome.html http://opencircuitdesign.com/qflow/welcome.html
WheelsAtLarge 10y ago
Question to all: is there a ycombinator for open source projects? Is it even possible to have one without profit as a motivator?
- niklasrde 10y ago
  YC does fund nonprofits. Also open source does not necessarily mean non profit.
- dragonwriter 10y ago
  > Question to all: is there a ycombinator for open source projects. I think it's called "YCombinator". > Is it even possible to have one without profit as a motivator? YC funds nonprofits, and open source, in any case, can (and often does) have a profit motive, so either way it seems YC would potentially be an option for an open source project.
throwayedidqo 10y ago
FPGA hardware is vendor locked and incredibly proprietary. The current business model sells chips at cost or below and makes it up with software licensing. This is a huge problem for open source adoption, and unless manufacturers change the business model we will never see widespread use of FPGA's.
- bcarlton0 10y ago
  As an FPGA designer, I can't disagree more with your statement of their business model. They make money on chips. That is indisputable. My last 3 designs used the vendor's free software, except for some IP we bought (IP=Intellectual property, a specific core). You might think of the IP as a library you would buy as a software engineer.
  - Ductapemaster 10y ago
    bcarlton0, what area of business are you in? I'm a young engineer working with FPGAs in the medical space and I'd love to hear about what else is out there.
    - bcarlton0 10y ago
      Ductapemaster, I have done designs in networking (e.g. packet processing and 10 Gb Ethernet), wireless (e.g. baseband part of a modem), glue logic, and other more specialized areas. FPGAs have a wide variety of uses other than ASIC prototyping and small glue logic.
  - throwayedidqo 10y ago
    The difference with software is that I don't need to buy the library to use the computer. Not sure which FPGA's you're using since all the big players force you to use their shitty tools and charge massive license fees for the privilege
    - bcarlton0 10y ago
      thowayedidoqo, I can still use them without the libraries. For example, I could write my own FFT or compression routine. It just may be cheaper to license them from the vendor or a third party. I have done plenty of designs without paid IP. I have used IP from Xilinx, Altera (pre-Intel), and third parties.
Ccecil 10y ago
Well there are some things like http://papilio.cc/ http://papilio.cc/ I personally backed the papilio duo kickstarter. I haven't done anything with the board yet but there has been some small stuff...and some pretty complex projects too.
wkoszek 10y ago
Good place to start this would be here: https://github.com/wkoszek/freebsd_netfpga https://github.com/wkoszek/freebsd_netfpga https://wiki.freebsd.org/FPGA/ https://wiki.freebsd.org/FPGA/ https://www.freshports.org/devel/xc3sprog/ https://www.freshports.org/devel/xc3sprog/ It's a FreeBSD NetFPGA driver for an older 1G card that I wrote during my internship 8 years ago, and a little ecosystem to make development more functional. I could program the FPGA from the FreeBSD and synthesize the code on FreeBSD that time. What you say is very hard, though. Speeds which are achieved with modern ASICs are hard to compete with, because ASICs do a lot of advanced stuff with DMAs, interrupts, checksum offloading. This might be doable with an expensive hardware, but nobody in DYI community has money to do this. Additionally the tools for synthesis are proprietary, and everything touching FPGA is pretty much proprietary too. Looking into date/author of the synthesis is as far as I could get: https://github.com/wkoszek/libxbf https://github.com/wkoszek/libxbf (can only open file and tell you where the bitstream starts; not what it actually is) So the road to complete freedom goes through ASIC world, in my opinion.
- canada_dry 10y ago
  Great list. I have Bunnie's awesome Novena, which came with an FPGA (as well as an SDR add-on). But, as the article says "FPGA development has always been an industrial activity, dominated by brutalist, opaque, and proprietary tools."... I haven't found the FPGA-FOR-DUMMIES guide to help me do anything with the thing.
  - wkoszek 10y ago
    Do you think there's a market for an FPGA-based tutorials? I think I have a good grasp of stuff necessary for this, but I always felt that it's a really niche business, even within the DYI/open-source community. If you want to start doing anything, I found it's best to look at the popularity of the board. S3E Starter Kit is by far the best, since most of the people could afford it, and it's nicely support. Any other board: case by case basis.
    - canada_dry 10y ago
Jhsto 10y ago
Unrelated to the article content, but the webpage zoom is broken on mobile.
tyingq 10y ago
Aside from the acceleration angle, the maker community would also benefit from a richer ecosystem around FPGAs, especially inexpensive ones. They are very handy for input and output of signals where you need precise timing. Things like oscilloscopes, video cards for vintage displays, driving led billboard modules, and so on. All of which either aren't possible, or aren't optimal/scalable on either Arduino or Rpi boards. There are also bits like drop in clones of atmega microcontrollers that run on the fpga, so you can leverage some of what you already know to interface with it.
cushychicken 10y ago
The author's example about a huge multitude of ethernet drivers doesn't really map well to the solution suggested (i.e. A big blank slate of FPGA logic with a bunch of ADC/DAC/codec fabric on the chip periphery). The wire side of Ethernet is really well specified, and tightly implemented. (Your chip won't be 802.3 compliant if it's not!) That's a result of really good specs on the IEEE's part. They put a TON of time into detailing how the Ethernet physical layer talks chip-to-chip. The driver side implementation for Ethernet, however, is basically the wild fucking West. There are cases where the author's approach makes sense - software defined radio jumps to mind. Adding one more layer of abstraction to ethernet drivers isn't one if them. That seems like an area where software could learn from hardware - namely, that good specs drive good implementations.
- donlzx 10y ago
  AFAIK, the digital interface of the physical layer (PHY) of the Ethernet stack are pretty much standardized (MII/RMII/GMII/RGMII). Most SOCs implement their own MAC layer, but are usually compatible with off-the-shelf PHY chips. The function and interface differences in proprietary MAC implementation is where the complexity of the kernel driver comes from. Suppose that we also standardized the interface between the MAC layer and the kernel and add an FPGA inside the existing PHY chip which is opened to real-time programming, a ton of optimization can be done. For example, DDOS packets could be thrown away well before reaching the kernel space. Previously I had done that with some low-cost FPGA kits, with less than 1K of HDL codes, it could get out only the IP packets wanted and then pass the packets directly to the application layer via the memory interface between the embedded CPU and FPGA logics. I think a programmable network interface is well worth the money if we care enough for openness and efficiency.
  - cushychicken 10y ago
    You're right - MII and it's derivatives are fairly standard. I agree that the MAC -> CPU interface is the root of a lot of the complexity that the author writes about. However, that still sort of serves to illustrate my point: the software to interface with the MAC is the chunk that introduces the most variability. Standardize that and a lot of your problems are solved. Integrating a bunch of analog/digital/vice versa fabric onto the same die is not a tenable solution to this particular issue. I'll admit the concept is mildly intriguing, but I think you'd find quickly that the silicon demands for a DAC/ADC of the quality needed to emulate any high speed waveform are a little out of reach fab wise. Too much space, not enough drive speed.
rubenfiszel 10y ago
For anyone interested in developping applications for FPGAs in a high-level DSL embedded in Scala, this project (https://github.com/stanford-ppl/spatial-lang https://github.com/stanford-ppl/spatial-lang) from a Stanford Lab might interest you. Disclaimer: I am part of the lab.
- spamizbad 10y ago
  I noticed there's a lot of RISC-V cores today implemented in Berkeley's Chisel (https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/). How would you say they compare?
  - rubenfiszel 10y ago
    Actually, Chisel is one of our main target codegen. We aim to be more high-level than Chisel. See here for a quick and very incomplete tour: http://spatial-lang.readthedocs.io/en/latest/tutorial.html http://spatial-lang.readthedocs.io/en/latest/tutorial.html
    - krapht 10y ago
      I was never able to convince my coworkers to program in FPGA HLLs, just because when you need to debug and simulate, you have to touch VHDL/Verilog in order to communicate with the board and understand what your high level abstraction is compiling to (not to mention the great deal of work that relies on tweaking and instantiating FPGA parameters like clock lines, buffers, DSP cells, etc). And actually this takes up the majority of the design time... so to make a software analogy, why bother writing in Scala when you have to verify and debug at at the assembly level?
      - smaddox 10y ago
        Is that a serious question? Because most software development is now done in high level languages. With the proper abstractions, there's no need to debug the high level code at the assembly level; you just need to debug the abstractions.
amboar 10y ago
TimVideos is an open source project using FPGAs and Python for conference (and other) video capture: https://hdmi2usb.tv/home/ https://hdmi2usb.tv/home/ So if you're interested in hardware, FPGAs or Python, it's a great opportunity to get hacking! They are also part of GSoC this year, but it might be too late to apply.
mindcrime 10y ago
Nice coincidental timing... I literally just ordered a Lattice Ice-40 eval board yesterday, and am hoping to get started using IceStorm to do some FPGA design stuff. It's all brand new to me, so any good entry level stuff, tutorials, docs, etc. on any of this stuff are very much appreciated.
- heathjohns 10y ago
  Author here - have a look at the main site, it was made just for that purpose: https://www.blinklight.io https://www.blinklight.io It's based around the iCE40/IceStorm, but it has its own specific "dev board". I'm planning on making it more generic later on.
fiziks_hckr 10y ago
Andrew Zonenberg has a whole list of open projects for FPGAs on his wiki: https://github.com/azonenberg/openfpga/wiki https://github.com/azonenberg/openfpga/wiki There has been a lot of exciting work in the same repo for Silego lines and general foundations for Open Source FPGA toolchains for many of the types out there. I've been really enjoying Clifford's Project IceStorm - open source tools which I've been using to develop/test on real hardware build up some Verilog chops: http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/ I made a quickstart for it in a repo here for those interested in starting some Verilog adventures : ) https://github.com/gskielian/TEAM-VERILOG https://github.com/gskielian/TEAM-VERILOG
michaelmior 10y ago
Since I didn't see any other good place to post feedback, I thought I would point out that it's "sheer number" not "shear number." Also, lowrisc.org is not accessible via HTTPS.
- heathjohns 10y ago
  Thank you, fixed!
  - michaelmior 10y ago
    Also, now that I've had time to start going through things, I wanted to add: great job! This seems like a pretty fantastic introduction so far. Although it might be helpful to provide solutions/additional hints in case someone gets stuck. (I'll admit I'm currently a little stuck at the "boss battle" in chapter 1.)
    - heathjohns 10y ago
      A sorry, I missed your comment! I'm currently working on getting a forum up so that people can help each other through challenges. In the meantime, if you're still stuck feel free to email me at heath@blinklight.io and I can give you some hints :)
visarga 10y ago
> FPGA development has always been an industrial activity, dominated by brutalist, opaque, and proprietary tools. Brutalist tools? As in, made out of raw concrete (béton brut)?
- duck2 10y ago
  Xilinx ISE does give the notion of raw concrete.
BillBohan 10y ago
I am currently waiting for my MATRIX Voice to arrive. https://www.indiegogo.com/projects/matrix-voice-open-source-voice-platform-for-all#/ https://www.indiegogo.com/projects/matrix-voice-open-source-... I have a Spartan 3AN dev board, another Spartan6 board, and an Arty. I was using Xilinx ISE free version to develop for the other boards until I bought the Arty. It came with a one year license for Vivado. I did not know that activating the Vivado license locked me in to developing only for Arty. ISE will no longer synthesize for any other target. I strongly dislike the closed nature of their software licensing. I am retired but the last 10 years I worked writing VHDL. I can kind of read Verilog and understand what it does but do not know it well enough to write in it. The systems I worked on were for oil well logging. My circuits went down a 16,800 ft. hole where it was 350° F and the pressure was over 7000 PSI. Production quantities were typically less than 100. We used no bigger an FPGA than was needed to keep power at a minimum as there was no way to dissipate heat. Also the circuit boards were quite small since they needed to fit into a housing less than 2" in diameter. Frequent design changes were needed but all ran on the same boards. I am currently working on a processor design that I call NISC. The set of all opcodes is the null set. It's a single instruction machine that does a move instruction with two operands, Source Address and Destination Address. I have considered putting the specifications and design on the internet as open source but am not sure where I should put it. Would anybody be interested in seeing it and where do you think I should put it?
- alnitak 10y ago
  Do it on Github!
  - BillBohan 10y ago
    OK https://github.com/BillBohan/NISC https://github.com/BillBohan/NISC
    - alnitak 10y ago
      Out of curiosity, what is the advantage of having a single instruction? I imagine that the benefit of a simple syntax in the assembly code is counterbalanced by the complexity of implementing complex logic, say control flows? Also, what is the performance impact of this approach? Wouldn't it cause more cycles for the same code in general, compared to multiple instructions? Lastly, could there be an optimized hardware for this set? (Executing directly on the RAM chipset maybe?) How do you see it perform against more traditional hardware?
forkandwait 10y ago
I am trying to teach myseful CUPL on Atmel 16v8's as a cheap, super basic way to get my feet wet in the FPGA/ CPLD/ GAL world. I have a breadboard half wired up to blink lights based on input, etc. I like older technology, but hope that what I learn applies to more modern FPGAs.
bsder 10y ago
Personally, I'd rather have the ability to create a chip for $5K. It's too stupidly expensive for the CAD tools (>$100K) when a wafer run is less than $20K for a very old process nowadays.
- petra 10y ago
  What about structured asic companies like eAsic and baysand ? don't they have a flow from fpga to a 65nm/45nm structured asic , starting at $70K ?
- smaddox 10y ago
  $5K wouldn't cover a single photomask, unless you're talking VERY OLD process. Maybe there are direct-write (laser or ebeam) litho foundries... I don't know.
  - neurotech1 10y ago
    Multi-Project Wafer [0] services like MOSIS [1] reduce the costs significantly. Not sure what the lowest practical budget for a project is, but $5k would be in the ballpark. Access to student licenses for design software is possible, too. [0] https://en.wikipedia.org/wiki/Multi-project_wafer_service https://en.wikipedia.org/wiki/Multi-project_wafer_service [1] https://www.mosis.com https://www.mosis.com
patsplat 10y ago
While tangential to the main point, it's weird to read about the failure of the open source phone knowing about the Android Open Source Project. What's missing from AOSP is Google Play Services aka proprietary web services. Open source has been a huge hit on the client, it's the firewalled server that has slowed the spread of free software.
jcoffland 10y ago
The Open-Source community needs Open-Source HDL compilers. Until this happens OSS for FPGAs will continue to be slow.
- grp 10y ago
  Like clash [0]? [0] http://www.clash-lang.org/ http://www.clash-lang.org/ ?
  - jcoffland 10y ago
    No. Clash is a transpiler from Haskel to other HDL languages. It still needs propritary compilers.
milesvp 10y ago
Having read through the comments, I'm surprised that no one is talking about the true benefit of a tech like fpga. It's that it's field programmable, with many that can be reprogrammed in fewer cycles than a cache miss. This means that ultimately, fpgas have the potential to be an optimization flag in your favorite compiler or jit. I see this as an inevitable convergence, especially when rumor of fpga transistors/mm^2 growing faster than cpu transistors/mm^2. What I can't tell is how much of what people talk about fpgas is hearsay, and how much is simply exaggerated. I know that every time I start to look into fpgas I always feel let down compared to their potential.
deleted 10y ago
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JoeNatter 10y ago
Hi there, we started a Kickstarter campaign a few days ago. We would really appreciate your expert feedback to our FPGA related board. Link: http://kck.st/2orXGCv http://kck.st/2orXGCv Our board connects a Raspberry Pi to the DE0 Nano. The FPGA can be programmed and reconfigured by the Raspberry Pi. The overall goal of our company is to make the entry to the FPGA world as easy as possible. Motivation for our connector board: We try to avoid the proprietary tools as much as possible. My experience with FPGAs so far (and only my opinions! please roast me) CASE 1: Only FPGA, no processor: To complex for bigger projects, because of the missing high abstraction layer. Drawbacks: Slow development process; To make something useful you need a lot of stuff in your FPGA. Very boring for beginners and in my opinion also for experts; CASE 2: FPGA with Soft-Core processor: For my bachelor thesis I once used the SCARTS Soft-Core processor from open cores in my DE0 Nano. Using an arbitrary Soft-Core processor from open cores can't be done Out-of-the-Box. You have to be quite experienced working with FPGAs. For my thesis for example I had to write my own SDRAM controller and add an additional pipeline stage to the processor. Drawbacks: Soft-Core processor quite slow; To hardcore for beginners; Simulation time makes you consume a lot of coffee; CASE 3: FPGA with processor on chip: Advantages: High speed interconnect between FPGA and processor; Fast processor; Disadvantages: Being fully dependent on the proprietary toolchains. In my opinion the "FPGA only"-tools suck, but the so-called "system builders/designers" drove me crazy; CASE 4: FPGA with external processor: In my opinion this is by far the best compromise. With some of my colleagues at the university I once made a bitcoin hashing cluster with our student boards. We also had an atmel microcontroller and a PC for that project. We just needed two days to make a fully working system. So FPGA programming can be very easy actually. But if you combine the Raspberry Pi and the DE0 Nano it should be even easier. With Raspberry Pi you have a clean and maintained Linux and with the DE0 Nano you have a powerful and still quite cheap FPGA board. Again I would really appreciate any feedback. What do you do with FPGAs and how do you approach bigger FPGA projects? Best regards, Joe
- gluggymug 10y ago
  Cool project. As someone from the FPGA industry, bigger projects just use your CASE 3 on a board to start prototyping. A Zedboard or similar. Cheaper version could be the Zybo. It's like $500 vs $200. When you get to production stage, you whip up your own board. What exactly is your complaint about the propriety tools? You are using Altera tools with the DE0 Nano.
jecel 10y ago
The course at that site is pretty interesting. There is an error that doesn't affect any of the examples but might be a problem for future circuits: what are called OR are actually XOR. It took me a while to figure it out because the notation for "don't care" was not obvious to me (it was explained later in the text after table circuits are introduced). I was able to build a circuit to test this by copying an OR to the display block and hooking up the inputs to the buttons and the output to column 1. It might be interesting to have some scheme to test sub-blocks directly.

309 points by heathjohns 10y ago

pryelluw 10y ago

Are there any fpga open hardware implementations available?

mlaretallack 10y ago
If you mean stuff that can run on FPGA's then https://opencores.org/ https://opencores.org/
- pryelluw 10y ago
  I also mean the actual hardware. :)
  - monocasa 10y ago
    This is the only project I know of. http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/
  - rvense 10y ago
    Quite sure the answer is no. There was a student project a while ago but it was more of a proof of concept. Open source chips of any kind are few and far between, and generally not at the cutting edge, technology-wise. Patents, as usual, will make this hard, before we even get to the economic aspects.
    - analognoise 10y ago
      I'd be more than happy with 1997-era (20 year patent expiry) FPGAs if they were open. Unfortunately, I don't think anyone else would.
      - rvense 10y ago
        Me too. For some things you need to be as fast or cheap or low-power or whatever as the competition to win, other times you just want to see how far you can go. At my hackerspace we've been mucking about with Clifford Wolf's PicoRV Risc-V implementation on Lattice Ice40 FPGAs lately. This'll give you something that's maybe on par with a lower-end ARM Cortex-M, plus the flexibility of the few thousand spare look-up tables. All open and hackable with open source tools (except for the actual FPGAs, mind). It's not much, but it's a start.
lvoudour 10y ago
None that I'm aware of. It would be a great leap as it would open the way for open source tools that go beyond netlist generation, but right now all major vendors keep their architecture proprietary and you need their tools to program their FPGAs
buildbot 10y ago
Actual chips, not as far as I know. There is a completely open source tool chain for a small FPGA, the icestorm project. The VPR project by university of Toronto has several architechure models defined, but there is probably no way to turn these into a real chip. FPGa vendors in general are extremely secretive about their designs. (I'm a grad student working in The FPGA space)
- zafka 10y ago
  > FPGa vendors in general are extremely secretive about their designs. That is the part that saddens me. I had always wanted to be able to play with the internal programming. Back when I started they were not anywhere as big, and we almost had visibility.
  - buildbot 10y ago
    At least with VPR you can define /modify your own FPGA architecture file! They are written in xml and parsed by the tool when doing place and route.

vvanders 10y ago

Something that's not really spoken to but is just as important is that FPGA development isn't software development. You're specifying hardware and usually that hardware doesn't just scale to new platforms. Time will tell if Open Source can make the transition over to that domain I'm cautiously optimistic but I think there's a larger cultural divide there than called out.

pryelluw 10y ago
Maybe we could have a hardware interface designed to be open?
- Sanddancer 10y ago
  For inter-IC interfaces, AMBA [1] and Wishbone [2] are open standards for connecting various sections of a chip --bridge between cpu, i/o bits, etc. External interfaces are also pretty open. A lot of FPGAs have dedicated logic for talking with a PCI bus, I2C bus, etc. Unless you're doing something extremely interesting and specialized, hardware's pretty open as is. [1] https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_A... [2] https://en.wikipedia.org/wiki/Wishbone_(computer_bus) https://en.wikipedia.org/wiki/Wishbone_(computer_bus)
pdelbarba 10y ago
It can and it can't. It's sort of like microcontroller code. You can define a core set of functions (like an FFT or something) that is very portable, but the peripheral mapping (which pins to output on, where resources are located, etc) is chip specific.
- vvanders 10y ago
  Yeah, even things like Block RAM, DSP units, carry + routing and other parts vary widely from chip/vendor.
blackguardx 10y ago
FPGAs are sexy to many people because they are exotic. Imagine a custom chip designed to do whatever you want and able to be reconfigured on the fly? The problem is that many aspiring learners want to approach it like a software problem. That can be a valid approach as long as they are willing to learn new abstractions. Many are not and then get frustrated and blame the tool ecosystem. Granted, the tool ecosystem does suck, but people (like me and others) are doing real work with these tools. Even if you scoff at FPGA tool quality, you have to remember that almost every ASIC out there was developed with similar (maybe slightly better) quality tools. There has to be flexibility on all sides. Tool vendors have to adapt to changing times (more open ecosystems) and software developers branching out into FPGAs have to be willing to learn how hardware works.

salesguy222 10y ago

Do FPGAs have a future beyond "prototyping non-memory intensive algorithms for eventual ASIC implementation"? It seems to me that the scale out + scale up method of x86 and GPUs are the most promising and profitable arenas still, besides some very niche and very particular applications? I could and would like to be wrong. I'd go learn FPGA dev then if there were things that needed accelerating and were personally lucrative to me :)

syntheticnature 10y ago
Sometimes they're good for "need ASIC-like results in a low-volume design" but that's more a special case of what you give, and of course the 'upgradable glue logic' case also is in play. I think the killer application would be to have programatically reconfigurable FPGAs that reconfigure on the fly to fit the needs, which has been discussed in various overhyped ways in the past, but I don't think the tooling is there. This effort might or might not make that possible -- imagine a chip where, say, the regex you're going to use to scan 1GB of data could be turned into an FPGA and then it just shovels the whole thing through a "HW" FIFO that detects matches much faster than a processor could. Nifty... but is it worth the effort to do?
- pdelbarba 10y ago
  You can kind of do this now if you want. The SOCs like the Cyclone V or Zinq have an arm core or two surrounded by FPGA fabric. The only barrier right now would be the dynamic reloading of the FPGA which I haven't seen done, but would be simple in principle (as opposed to having a soft core that would likely have it's state interrupted if you re-flashed everything)
  - aseipp 10y ago
    Most newer Intel (Cyclone and beyond) and Xilinx (-7 series) support various levels of partial logic reconfiguration. If you plan your device layout right, you can simply reprogram a region of fabric that is hardwired wired to the 'shell' of your system (which is connected to the peripherials). If you have setups like Vivado's SDSoC/high-level synthesis, you can do things like dynamically reconfigure OpenCL kernels, etc. Of course, the problem is synthesis, verification, testing etc is all rather difficult in practice and takes a long time. The boards themselves also can't do synthesis/compilation, obviously, since they're fairly limited and it's a time-consuming process. You'd have to make it act more like an OTA update system, but that comes with a lot of its own problems...

zafka 10y ago

I love FPGAs in a simplistic sort of way. I first started working with them when I was in school (1994-96) and thought I was going to spend my life with them. Other than some simulations with very expensive software that had been donated by Motorola I never actually used FPGAs. But from when I first started looking at them, I thought they would be the building blocks for an AI machine that could be added on to forever. I still think so, but I thought that there would be more visibility into the internal workings of the chips.

PhaseLockk 10y ago

I'm not exactly clear on what the post is advocating. If it's saying that there should be an open source implementation of an FPGA, then I just have to say that I think there's no way that's happening anytime soon. There are way too many hurdles. If the argument is just that the open source community should leverage FPGAs more as a means of creating more powerful "open source" hardware, and that there should be more resources for people to learn how to write hardware, then I guess I agree with that. But I don't think FPGAs will be the panacea the author seems to think they will. FPGA implementations will always entail a performance and/or efficiency hit compared to ASIC implementations, and I think many people won't want to take that hit, limiting the number of users who are willing to adopt the open source solutions.

heathjohns 10y ago
Author here - I'm advocating the latter. I agree with you to a point. However, I believe that those things that have been with us for decades: sound cards, 2D graphics adaptors, network cards, etc. can be done in FPGAs, and should be. The speed is there, and the power used by the southbridge and peripherals is eclipsed by the processor and the screen backlight, so I don't think the power consumption is worth worrying about (I'd be interested to see evidence to the contrary, though). Put another way: much of the foundational chips on motherboard are no long performance-sensitive, so we shouldn't be paying a compatibility price for it.
- petra 10y ago
  Why not just choose a small set of "golden" chips, create high quality drivers that abstract away incompatibilities if possible, and verify the heck out of that ?
  - heathjohns 10y ago
    The trouble with "golden" chips is a) the manufacturer can EOL it at any time (and I don't think just the OSS people are numerous enough to keep any specific set in production), and b) it freezes things in time. For things that don't change much (e.g. sound cards), no problem, but there's still improvements to be made in other areas. The focus for FPGAs has traditionally been performance, but I think there's a model where they can be used for both long-lived compatibility and cutting-edge devices living together on the same chip.

nickpsecurity 10y ago

The trick is getting more EE's to spend their grants on open-source FPGA's and tooling: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.html https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-... http://opencircuitdesign.com/qflow/welcome.html http://opencircuitdesign.com/qflow/welcome.html

WheelsAtLarge 10y ago

Question to all: is there a ycombinator for open source projects? Is it even possible to have one without profit as a motivator?

niklasrde 10y ago
YC does fund nonprofits. Also open source does not necessarily mean non profit.
dragonwriter 10y ago
> Question to all: is there a ycombinator for open source projects. I think it's called "YCombinator". > Is it even possible to have one without profit as a motivator? YC funds nonprofits, and open source, in any case, can (and often does) have a profit motive, so either way it seems YC would potentially be an option for an open source project.

throwayedidqo 10y ago

FPGA hardware is vendor locked and incredibly proprietary. The current business model sells chips at cost or below and makes it up with software licensing. This is a huge problem for open source adoption, and unless manufacturers change the business model we will never see widespread use of FPGA's.

bcarlton0 10y ago
As an FPGA designer, I can't disagree more with your statement of their business model. They make money on chips. That is indisputable. My last 3 designs used the vendor's free software, except for some IP we bought (IP=Intellectual property, a specific core). You might think of the IP as a library you would buy as a software engineer.
- Ductapemaster 10y ago
  bcarlton0, what area of business are you in? I'm a young engineer working with FPGAs in the medical space and I'd love to hear about what else is out there.
  - bcarlton0 10y ago
    Ductapemaster, I have done designs in networking (e.g. packet processing and 10 Gb Ethernet), wireless (e.g. baseband part of a modem), glue logic, and other more specialized areas. FPGAs have a wide variety of uses other than ASIC prototyping and small glue logic.
- throwayedidqo 10y ago
  The difference with software is that I don't need to buy the library to use the computer. Not sure which FPGA's you're using since all the big players force you to use their shitty tools and charge massive license fees for the privilege
  - bcarlton0 10y ago
    thowayedidoqo, I can still use them without the libraries. For example, I could write my own FFT or compression routine. It just may be cheaper to license them from the vendor or a third party. I have done plenty of designs without paid IP. I have used IP from Xilinx, Altera (pre-Intel), and third parties.

Ccecil 10y ago

Well there are some things like http://papilio.cc/ http://papilio.cc/ I personally backed the papilio duo kickstarter. I haven't done anything with the board yet but there has been some small stuff...and some pretty complex projects too.

wkoszek 10y ago

Good place to start this would be here: https://github.com/wkoszek/freebsd_netfpga https://github.com/wkoszek/freebsd_netfpga https://wiki.freebsd.org/FPGA/ https://wiki.freebsd.org/FPGA/ https://www.freshports.org/devel/xc3sprog/ https://www.freshports.org/devel/xc3sprog/ It's a FreeBSD NetFPGA driver for an older 1G card that I wrote during my internship 8 years ago, and a little ecosystem to make development more functional. I could program the FPGA from the FreeBSD and synthesize the code on FreeBSD that time. What you say is very hard, though. Speeds which are achieved with modern ASICs are hard to compete with, because ASICs do a lot of advanced stuff with DMAs, interrupts, checksum offloading. This might be doable with an expensive hardware, but nobody in DYI community has money to do this. Additionally the tools for synthesis are proprietary, and everything touching FPGA is pretty much proprietary too. Looking into date/author of the synthesis is as far as I could get: https://github.com/wkoszek/libxbf https://github.com/wkoszek/libxbf (can only open file and tell you where the bitstream starts; not what it actually is) So the road to complete freedom goes through ASIC world, in my opinion.

canada_dry 10y ago
Great list. I have Bunnie's awesome Novena, which came with an FPGA (as well as an SDR add-on). But, as the article says "FPGA development has always been an industrial activity, dominated by brutalist, opaque, and proprietary tools."... I haven't found the FPGA-FOR-DUMMIES guide to help me do anything with the thing.
- wkoszek 10y ago
  Do you think there's a market for an FPGA-based tutorials? I think I have a good grasp of stuff necessary for this, but I always felt that it's a really niche business, even within the DYI/open-source community. If you want to start doing anything, I found it's best to look at the popularity of the board. S3E Starter Kit is by far the best, since most of the people could afford it, and it's nicely support. Any other board: case by case basis.
  - canada_dry 10y ago

Jhsto 10y ago

Unrelated to the article content, but the webpage zoom is broken on mobile.

tyingq 10y ago

Aside from the acceleration angle, the maker community would also benefit from a richer ecosystem around FPGAs, especially inexpensive ones. They are very handy for input and output of signals where you need precise timing. Things like oscilloscopes, video cards for vintage displays, driving led billboard modules, and so on. All of which either aren't possible, or aren't optimal/scalable on either Arduino or Rpi boards. There are also bits like drop in clones of atmega microcontrollers that run on the fpga, so you can leverage some of what you already know to interface with it.

cushychicken 10y ago

The author's example about a huge multitude of ethernet drivers doesn't really map well to the solution suggested (i.e. A big blank slate of FPGA logic with a bunch of ADC/DAC/codec fabric on the chip periphery). The wire side of Ethernet is really well specified, and tightly implemented. (Your chip won't be 802.3 compliant if it's not!) That's a result of really good specs on the IEEE's part. They put a TON of time into detailing how the Ethernet physical layer talks chip-to-chip. The driver side implementation for Ethernet, however, is basically the wild fucking West. There are cases where the author's approach makes sense - software defined radio jumps to mind. Adding one more layer of abstraction to ethernet drivers isn't one if them. That seems like an area where software could learn from hardware - namely, that good specs drive good implementations.

donlzx 10y ago
AFAIK, the digital interface of the physical layer (PHY) of the Ethernet stack are pretty much standardized (MII/RMII/GMII/RGMII). Most SOCs implement their own MAC layer, but are usually compatible with off-the-shelf PHY chips. The function and interface differences in proprietary MAC implementation is where the complexity of the kernel driver comes from. Suppose that we also standardized the interface between the MAC layer and the kernel and add an FPGA inside the existing PHY chip which is opened to real-time programming, a ton of optimization can be done. For example, DDOS packets could be thrown away well before reaching the kernel space. Previously I had done that with some low-cost FPGA kits, with less than 1K of HDL codes, it could get out only the IP packets wanted and then pass the packets directly to the application layer via the memory interface between the embedded CPU and FPGA logics. I think a programmable network interface is well worth the money if we care enough for openness and efficiency.
- cushychicken 10y ago
  You're right - MII and it's derivatives are fairly standard. I agree that the MAC -> CPU interface is the root of a lot of the complexity that the author writes about. However, that still sort of serves to illustrate my point: the software to interface with the MAC is the chunk that introduces the most variability. Standardize that and a lot of your problems are solved. Integrating a bunch of analog/digital/vice versa fabric onto the same die is not a tenable solution to this particular issue. I'll admit the concept is mildly intriguing, but I think you'd find quickly that the silicon demands for a DAC/ADC of the quality needed to emulate any high speed waveform are a little out of reach fab wise. Too much space, not enough drive speed.

rubenfiszel 10y ago

For anyone interested in developping applications for FPGAs in a high-level DSL embedded in Scala, this project (https://github.com/stanford-ppl/spatial-lang https://github.com/stanford-ppl/spatial-lang) from a Stanford Lab might interest you. Disclaimer: I am part of the lab.

spamizbad 10y ago
I noticed there's a lot of RISC-V cores today implemented in Berkeley's Chisel (https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/). How would you say they compare?
- rubenfiszel 10y ago
  Actually, Chisel is one of our main target codegen. We aim to be more high-level than Chisel. See here for a quick and very incomplete tour: http://spatial-lang.readthedocs.io/en/latest/tutorial.html http://spatial-lang.readthedocs.io/en/latest/tutorial.html
  - krapht 10y ago
    I was never able to convince my coworkers to program in FPGA HLLs, just because when you need to debug and simulate, you have to touch VHDL/Verilog in order to communicate with the board and understand what your high level abstraction is compiling to (not to mention the great deal of work that relies on tweaking and instantiating FPGA parameters like clock lines, buffers, DSP cells, etc). And actually this takes up the majority of the design time... so to make a software analogy, why bother writing in Scala when you have to verify and debug at at the assembly level?
    - smaddox 10y ago
      Is that a serious question? Because most software development is now done in high level languages. With the proper abstractions, there's no need to debug the high level code at the assembly level; you just need to debug the abstractions.

amboar 10y ago

TimVideos is an open source project using FPGAs and Python for conference (and other) video capture: https://hdmi2usb.tv/home/ https://hdmi2usb.tv/home/ So if you're interested in hardware, FPGAs or Python, it's a great opportunity to get hacking! They are also part of GSoC this year, but it might be too late to apply.

mindcrime 10y ago

Nice coincidental timing... I literally just ordered a Lattice Ice-40 eval board yesterday, and am hoping to get started using IceStorm to do some FPGA design stuff. It's all brand new to me, so any good entry level stuff, tutorials, docs, etc. on any of this stuff are very much appreciated.

heathjohns 10y ago
Author here - have a look at the main site, it was made just for that purpose: https://www.blinklight.io https://www.blinklight.io It's based around the iCE40/IceStorm, but it has its own specific "dev board". I'm planning on making it more generic later on.

fiziks_hckr 10y ago

Andrew Zonenberg has a whole list of open projects for FPGAs on his wiki: https://github.com/azonenberg/openfpga/wiki https://github.com/azonenberg/openfpga/wiki There has been a lot of exciting work in the same repo for Silego lines and general foundations for Open Source FPGA toolchains for many of the types out there. I've been really enjoying Clifford's Project IceStorm - open source tools which I've been using to develop/test on real hardware build up some Verilog chops: http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/ I made a quickstart for it in a repo here for those interested in starting some Verilog adventures : ) https://github.com/gskielian/TEAM-VERILOG https://github.com/gskielian/TEAM-VERILOG

michaelmior 10y ago

Since I didn't see any other good place to post feedback, I thought I would point out that it's "sheer number" not "shear number." Also, lowrisc.org is not accessible via HTTPS.

heathjohns 10y ago
Thank you, fixed!
- michaelmior 10y ago
  Also, now that I've had time to start going through things, I wanted to add: great job! This seems like a pretty fantastic introduction so far. Although it might be helpful to provide solutions/additional hints in case someone gets stuck. (I'll admit I'm currently a little stuck at the "boss battle" in chapter 1.)
  - heathjohns 10y ago
    A sorry, I missed your comment! I'm currently working on getting a forum up so that people can help each other through challenges. In the meantime, if you're still stuck feel free to email me at heath@blinklight.io and I can give you some hints :)

visarga 10y ago

> FPGA development has always been an industrial activity, dominated by brutalist, opaque, and proprietary tools. Brutalist tools? As in, made out of raw concrete (béton brut)?

duck2 10y ago
Xilinx ISE does give the notion of raw concrete.

BillBohan 10y ago

I am currently waiting for my MATRIX Voice to arrive. https://www.indiegogo.com/projects/matrix-voice-open-source-voice-platform-for-all#/ https://www.indiegogo.com/projects/matrix-voice-open-source-... I have a Spartan 3AN dev board, another Spartan6 board, and an Arty. I was using Xilinx ISE free version to develop for the other boards until I bought the Arty. It came with a one year license for Vivado. I did not know that activating the Vivado license locked me in to developing only for Arty. ISE will no longer synthesize for any other target. I strongly dislike the closed nature of their software licensing. I am retired but the last 10 years I worked writing VHDL. I can kind of read Verilog and understand what it does but do not know it well enough to write in it. The systems I worked on were for oil well logging. My circuits went down a 16,800 ft. hole where it was 350° F and the pressure was over 7000 PSI. Production quantities were typically less than 100. We used no bigger an FPGA than was needed to keep power at a minimum as there was no way to dissipate heat. Also the circuit boards were quite small since they needed to fit into a housing less than 2" in diameter. Frequent design changes were needed but all ran on the same boards. I am currently working on a processor design that I call NISC. The set of all opcodes is the null set. It's a single instruction machine that does a move instruction with two operands, Source Address and Destination Address. I have considered putting the specifications and design on the internet as open source but am not sure where I should put it. Would anybody be interested in seeing it and where do you think I should put it?

alnitak 10y ago
Do it on Github!
- BillBohan 10y ago
  OK https://github.com/BillBohan/NISC https://github.com/BillBohan/NISC
  - alnitak 10y ago
    Out of curiosity, what is the advantage of having a single instruction? I imagine that the benefit of a simple syntax in the assembly code is counterbalanced by the complexity of implementing complex logic, say control flows? Also, what is the performance impact of this approach? Wouldn't it cause more cycles for the same code in general, compared to multiple instructions? Lastly, could there be an optimized hardware for this set? (Executing directly on the RAM chipset maybe?) How do you see it perform against more traditional hardware?

forkandwait 10y ago

I am trying to teach myseful CUPL on Atmel 16v8's as a cheap, super basic way to get my feet wet in the FPGA/ CPLD/ GAL world. I have a breadboard half wired up to blink lights based on input, etc. I like older technology, but hope that what I learn applies to more modern FPGAs.

bsder 10y ago

Personally, I'd rather have the ability to create a chip for $5K. It's too stupidly expensive for the CAD tools (>$100K) when a wafer run is less than $20K for a very old process nowadays.

petra 10y ago
What about structured asic companies like eAsic and baysand ? don't they have a flow from fpga to a 65nm/45nm structured asic , starting at $70K ?
smaddox 10y ago
$5K wouldn't cover a single photomask, unless you're talking VERY OLD process. Maybe there are direct-write (laser or ebeam) litho foundries... I don't know.
- neurotech1 10y ago
  Multi-Project Wafer [0] services like MOSIS [1] reduce the costs significantly. Not sure what the lowest practical budget for a project is, but $5k would be in the ballpark. Access to student licenses for design software is possible, too. [0] https://en.wikipedia.org/wiki/Multi-project_wafer_service https://en.wikipedia.org/wiki/Multi-project_wafer_service [1] https://www.mosis.com https://www.mosis.com

patsplat 10y ago

While tangential to the main point, it's weird to read about the failure of the open source phone knowing about the Android Open Source Project. What's missing from AOSP is Google Play Services aka proprietary web services. Open source has been a huge hit on the client, it's the firewalled server that has slowed the spread of free software.

jcoffland 10y ago

The Open-Source community needs Open-Source HDL compilers. Until this happens OSS for FPGAs will continue to be slow.

grp 10y ago
Like clash [0]? [0] http://www.clash-lang.org/ http://www.clash-lang.org/ ?
- jcoffland 10y ago
  No. Clash is a transpiler from Haskel to other HDL languages. It still needs propritary compilers.

milesvp 10y ago

Having read through the comments, I'm surprised that no one is talking about the true benefit of a tech like fpga. It's that it's field programmable, with many that can be reprogrammed in fewer cycles than a cache miss. This means that ultimately, fpgas have the potential to be an optimization flag in your favorite compiler or jit. I see this as an inevitable convergence, especially when rumor of fpga transistors/mm^2 growing faster than cpu transistors/mm^2. What I can't tell is how much of what people talk about fpgas is hearsay, and how much is simply exaggerated. I know that every time I start to look into fpgas I always feel let down compared to their potential.

deleted 10y ago

[deleted]

JoeNatter 10y ago

Hi there, we started a Kickstarter campaign a few days ago. We would really appreciate your expert feedback to our FPGA related board. Link: http://kck.st/2orXGCv http://kck.st/2orXGCv Our board connects a Raspberry Pi to the DE0 Nano. The FPGA can be programmed and reconfigured by the Raspberry Pi. The overall goal of our company is to make the entry to the FPGA world as easy as possible. Motivation for our connector board: We try to avoid the proprietary tools as much as possible. My experience with FPGAs so far (and only my opinions! please roast me) CASE 1: Only FPGA, no processor: To complex for bigger projects, because of the missing high abstraction layer. Drawbacks: Slow development process; To make something useful you need a lot of stuff in your FPGA. Very boring for beginners and in my opinion also for experts; CASE 2: FPGA with Soft-Core processor: For my bachelor thesis I once used the SCARTS Soft-Core processor from open cores in my DE0 Nano. Using an arbitrary Soft-Core processor from open cores can't be done Out-of-the-Box. You have to be quite experienced working with FPGAs. For my thesis for example I had to write my own SDRAM controller and add an additional pipeline stage to the processor. Drawbacks: Soft-Core processor quite slow; To hardcore for beginners; Simulation time makes you consume a lot of coffee; CASE 3: FPGA with processor on chip: Advantages: High speed interconnect between FPGA and processor; Fast processor; Disadvantages: Being fully dependent on the proprietary toolchains. In my opinion the "FPGA only"-tools suck, but the so-called "system builders/designers" drove me crazy; CASE 4: FPGA with external processor: In my opinion this is by far the best compromise. With some of my colleagues at the university I once made a bitcoin hashing cluster with our student boards. We also had an atmel microcontroller and a PC for that project. We just needed two days to make a fully working system. So FPGA programming can be very easy actually. But if you combine the Raspberry Pi and the DE0 Nano it should be even easier. With Raspberry Pi you have a clean and maintained Linux and with the DE0 Nano you have a powerful and still quite cheap FPGA board. Again I would really appreciate any feedback. What do you do with FPGAs and how do you approach bigger FPGA projects? Best regards, Joe

gluggymug 10y ago
Cool project. As someone from the FPGA industry, bigger projects just use your CASE 3 on a board to start prototyping. A Zedboard or similar. Cheaper version could be the Zybo. It's like $500 vs $200. When you get to production stage, you whip up your own board. What exactly is your complaint about the propriety tools? You are using Altera tools with the DE0 Nano.

jecel 10y ago

The course at that site is pretty interesting. There is an error that doesn't affect any of the examples but might be a problem for future circuits: what are called OR are actually XOR. It took me a while to figure it out because the notation for "don't care" was not obvious to me (it was explained later in the text after table circuits are introduced). I was able to build a circuit to test this by copying an OR to the display block and hooking up the inputs to the buttons and the output to column 1. It might be interesting to have some scheme to test sub-blocks directly.