5 ms·

I think we also forget that frequency does not mean CPU power.

by gravypod 10y ago

vbezhenar 10y ago
Why not? All things being equal, higher frequency allows to do more operations/s.
- sesqu 10y ago
  The basic idea is that all things don't remain equal. Some of the differences that can and do dominate frequency differences are the microarchitecture, resulting in machine instructions that aren't comparable even if both processors have a similar frequency, parallelism, resulting in a variable amount of instructions handled per clock cycle, and data transfer, resulting in clock cycles being wasted. GP argues that even though frequency has not increased recently, performance has, a point better made by the article.
- ayrx 10y ago
  But all things are not equal.
- gravypod 10y ago
  All things are not equal. Different architectures and pipeline setups result in completely different outcomes. Frequency is far from an accurate measure of performance. It doesn't take in IO, context switching, pipe lining, interrupts, and multicore systems. Even within the same family clock speed may not have much to do with performance. Clock speed is just a measure of how many times a second some increment in an operation may occur. Doesn't mean it will increment it's progress in an operation, doesn't mean the operation can't happen between then, it just means the CPU will find out about the state of that between those updates. You also need to take into account the BPU and the vector math sections of the die which this sort of metric completely ignores.
- lordnacho 10y ago
  This is true if you can always be calculating. You can't. For instance, CPUs have sped up a lot compared to memory. As a result, if you just calculate as fast as you can, you run out of data to calculate on. Suddenly it becomes more relevant how fast you can access memory. So now we have all sorts of complicated cache mechanisms to help us keep the data to hand. Coding needs to be cache friendly as well. If you look at CPU prices, you can see the amount of cache increases with the price.
  - userbinator 10y ago
    Also important to keep in mind is that the "data" also includes instructions --- and running out of instructions to execute is even worse than data; with things like OoO and superscalar, the CPU can still keep going with executing "around" instructions that are waiting for data, but only as long as it can continue fetching instructions.
- nom 10y ago
  Exactly. If you increase the clock frequency you will get more ops/s out of the CPU, everyone can see that easily. The only problem is that the anmount of electrons you have to push through the transistors has a quadratic* dependence on frequency. However, It's also clear what gravypod is trying to say. The architecture itself has a greater influence on the "processing power" nowadays because the clock has reached physical limits and can't be increased much further without getting expensive (see IBM Power Sytems). Bottomline is that you can't compare CPUs by frequency alone, but it was never any different, the architectures 15 years ago just sucked so hard that all of them were too similar regarding instructions per cycle. I think we can blame AMD for that line of thinking, they had to push hard against Intel during a time where everyone used clock frequency to compare CPUs. *edit: Sorry I remembered it wrong, the commonly used power equation is P = C x V^2 x f (capacity, voltage, frequency). Power is linear dependent on the frequency!
  - static_noise 10y ago
    > The only problem is that the anmount of electrons you have to push through the transistors has a quadratic dependence on frequency. I don't see how this is ultimately true. The amount of electrons needed to flip a capacitor is constant given that the voltage is constant. The more often you flip, the more current you need per time. The amount of electrons needed to flip a capacitor is proportional to the voltage. So, lower voltage means a) less power per electron and b) less electrons. Therefore the power is quadratic with the operating voltage. Third, if you want to increase the frequency, at some point, you have to increase the voltage or you get errors. Then you increase frequency and voltage at the same time and your power consumption shoots up.
    - nom 10y ago
      Hmm maybe I'm wrong. I vividly remember an equation for the power consumption of a CPU, and it definitely had a f^2 in it. However, I currently can't derive it anymore (and it was definitely a simplification). I'll try to pull up the slides later. It's probably outdated, the influence of the individual factors may have changed. In the meantime I can only offer this [1] stackexchange post. Power of a CPU is definitely quadratic in f, or even worse. [1] http://physics.stackexchange.com/questions/34766/how-does-power-consumption-vary-with-the-processor-frequency-in-a-typical-comput http://physics.stackexchange.com/questions/34766/how-does-po... edit: I probably remembered it wrong and I now think that that the equation was P=C x V^2 x f. However, transition power effectively has an exponent much greater than 2, but that's apparently caused by the increased die temperature (according to the post on Anandtech).
- biofox 10y ago
  The shortcoming of clock frequency as a performance measure is illustrated by comparing Instructions per Second (MIPS) [1]. e.g. ARM Cortex A7: 2,850 MIPS at 1.5 GHz Qualcomm Krait (Cortex A15-like, 2-core): 9,900 MIPS at 1.5 GHz Both processors have the same clock frequency, but one has over three times the processing speed in MIPS. [1] https://en.wikipedia.org/wiki/Instructions_per_second#Timeline_of_instructions_per_second https://en.wikipedia.org/wiki/Instructions_per_second#Timeli...
  - static_noise 10y ago
    Does this hold true for algorithms which are hard to parallelize because everything depends on intermediate results which are hard to predict?
    - biofox 10y ago
      As others have said below, issues that have little to do with parallelisation can heavily influence performance, e.g. caching and I/O. Referring to the list on wikipedia again, compare two different 4-core CPUs: Intel Core i5-2500K 4-core: 83,000 MIPS at 3.3 GHz Intel Core i7 875K: 92,100 MIPS at 2.93 GHz
      - static_noise 10y ago
        I'll have to repeat my question in other words. How many MIPS do you think, remain, if every third instruction is a mispredicted branch and every second memory access is a cache miss? Modern CPUs use pipelining which executes many instructions parallel. This only works well if everything goes as predicted. If you have an algorithm which works contrary to what the branch prediction thinks and a cache which does not hold the data you need, your performance goes down the drain. Those MIPS mean nothing if not put into the right context.
        Dylan16807 10y ago
        You can do a lot to work around branches. Cache misses make CPU speed irrelevant, but when you look at your memory system it's another instance of the same problem with the same tradeoffs of frequency vs. work per cycle. And when the "right context" is waiting for the outside world, that's not the most important context.
- disposablezero 10y ago
  Frequency tends to be somewhat orthogonal to instructions per watt. (It's easish to build hyperpipelined CPUs which have horrendous pipeline stall latency characteristics.) And CMOS tends to dissipate power (most as heat) proportional to the square of the frequency because zero crossing in CMOS logic is a virtual short-circuit. MIPS (the former Hennessy shop), SPARC and other RISC shops tended to ignore more/less the retail consumerization of the CISC MHz wars to bet on architecture fundamentals. I highly recommend taking a digital logic and computer architecture class in a CS program to understand how pipelines/instruction units are laid out (microcoding, branch prediction, pipeline stalls, macro ISA, etc.), what makes them fast/slow and challenges to implementation.
  - wyager 10y ago
    One thing that surprised me while taking a processor design course is that pipelining is actually old technology; modern processors are essentially partially nonlinear graph-reduction machines. Your average CPU core might have 6-10 different logic units (multiple ALUs, FPUs, MUs, etc.) possibly shared across 2 "hyperthreaded" virtual cores. This means that if the incoming assembly code is fairly linear (or has no mispredicted branches) and has some partially independent computation, you could feasibly sustain 5+ full instructions per cycle. As a side note, the Tomasulo algorithm is a huge pain in the ass to do in hardware. Props to the processor engineers who are implementing modern OOO execution hardware in whatever awful proprietary HDL/IDE combo your company makes you use.
    - dom0 10y ago
      Oh yes they do. A really excellent example here are ARX (add rotate xor) algorithms in cryptography. Take BLAKE2 for example; the reference C code, compiled to plain x86-64 assembly mainly consists of long rows of addq/xorq/rorq instructions. A modern CPU manages to schedule these so efficiently that the performance difference to a hand-coded SSE or AVX version practically never matters. If you take a peek at Haswell's port map (eg. http://images.anandtech.com/reviews/cpu/intel/Haswell/Architecture/haswellexec.png http://images.anandtech.com/reviews/cpu/intel/Haswell/Archit... ) you'll see that there are four out of eight ports who can do integer arx operations. Since memory and addr ops got their own ports this means that even the straight addq/xorq/rorq code can almost fully utilize the core. This is no accident, though, the algorithm was designed to take advantage of designs like this :)

I think we also forget that frequency does not mean CPU power.

vbezhenar 10y ago

Why not? All things being equal, higher frequency allows to do more operations/s.

sesqu 10y ago
The basic idea is that all things don't remain equal. Some of the differences that can and do dominate frequency differences are the microarchitecture, resulting in machine instructions that aren't comparable even if both processors have a similar frequency, parallelism, resulting in a variable amount of instructions handled per clock cycle, and data transfer, resulting in clock cycles being wasted. GP argues that even though frequency has not increased recently, performance has, a point better made by the article.
ayrx 10y ago
But all things are not equal.
gravypod 10y ago
All things are not equal. Different architectures and pipeline setups result in completely different outcomes. Frequency is far from an accurate measure of performance. It doesn't take in IO, context switching, pipe lining, interrupts, and multicore systems. Even within the same family clock speed may not have much to do with performance. Clock speed is just a measure of how many times a second some increment in an operation may occur. Doesn't mean it will increment it's progress in an operation, doesn't mean the operation can't happen between then, it just means the CPU will find out about the state of that between those updates. You also need to take into account the BPU and the vector math sections of the die which this sort of metric completely ignores.
lordnacho 10y ago
This is true if you can always be calculating. You can't. For instance, CPUs have sped up a lot compared to memory. As a result, if you just calculate as fast as you can, you run out of data to calculate on. Suddenly it becomes more relevant how fast you can access memory. So now we have all sorts of complicated cache mechanisms to help us keep the data to hand. Coding needs to be cache friendly as well. If you look at CPU prices, you can see the amount of cache increases with the price.
- userbinator 10y ago
  Also important to keep in mind is that the "data" also includes instructions --- and running out of instructions to execute is even worse than data; with things like OoO and superscalar, the CPU can still keep going with executing "around" instructions that are waiting for data, but only as long as it can continue fetching instructions.
nom 10y ago
Exactly. If you increase the clock frequency you will get more ops/s out of the CPU, everyone can see that easily. The only problem is that the anmount of electrons you have to push through the transistors has a quadratic* dependence on frequency. However, It's also clear what gravypod is trying to say. The architecture itself has a greater influence on the "processing power" nowadays because the clock has reached physical limits and can't be increased much further without getting expensive (see IBM Power Sytems). Bottomline is that you can't compare CPUs by frequency alone, but it was never any different, the architectures 15 years ago just sucked so hard that all of them were too similar regarding instructions per cycle. I think we can blame AMD for that line of thinking, they had to push hard against Intel during a time where everyone used clock frequency to compare CPUs. *edit: Sorry I remembered it wrong, the commonly used power equation is P = C x V^2 x f (capacity, voltage, frequency). Power is linear dependent on the frequency!
- static_noise 10y ago
  > The only problem is that the anmount of electrons you have to push through the transistors has a quadratic dependence on frequency. I don't see how this is ultimately true. The amount of electrons needed to flip a capacitor is constant given that the voltage is constant. The more often you flip, the more current you need per time. The amount of electrons needed to flip a capacitor is proportional to the voltage. So, lower voltage means a) less power per electron and b) less electrons. Therefore the power is quadratic with the operating voltage. Third, if you want to increase the frequency, at some point, you have to increase the voltage or you get errors. Then you increase frequency and voltage at the same time and your power consumption shoots up.
  - nom 10y ago
    Hmm maybe I'm wrong. I vividly remember an equation for the power consumption of a CPU, and it definitely had a f^2 in it. However, I currently can't derive it anymore (and it was definitely a simplification). I'll try to pull up the slides later. It's probably outdated, the influence of the individual factors may have changed. In the meantime I can only offer this [1] stackexchange post. Power of a CPU is definitely quadratic in f, or even worse. [1] http://physics.stackexchange.com/questions/34766/how-does-power-consumption-vary-with-the-processor-frequency-in-a-typical-comput http://physics.stackexchange.com/questions/34766/how-does-po... edit: I probably remembered it wrong and I now think that that the equation was P=C x V^2 x f. However, transition power effectively has an exponent much greater than 2, but that's apparently caused by the increased die temperature (according to the post on Anandtech).
biofox 10y ago
The shortcoming of clock frequency as a performance measure is illustrated by comparing Instructions per Second (MIPS) [1]. e.g. ARM Cortex A7: 2,850 MIPS at 1.5 GHz Qualcomm Krait (Cortex A15-like, 2-core): 9,900 MIPS at 1.5 GHz Both processors have the same clock frequency, but one has over three times the processing speed in MIPS. [1] https://en.wikipedia.org/wiki/Instructions_per_second#Timeline_of_instructions_per_second https://en.wikipedia.org/wiki/Instructions_per_second#Timeli...
- static_noise 10y ago
  Does this hold true for algorithms which are hard to parallelize because everything depends on intermediate results which are hard to predict?
  - biofox 10y ago
    As others have said below, issues that have little to do with parallelisation can heavily influence performance, e.g. caching and I/O. Referring to the list on wikipedia again, compare two different 4-core CPUs: Intel Core i5-2500K 4-core: 83,000 MIPS at 3.3 GHz Intel Core i7 875K: 92,100 MIPS at 2.93 GHz
    - static_noise 10y ago
      I'll have to repeat my question in other words. How many MIPS do you think, remain, if every third instruction is a mispredicted branch and every second memory access is a cache miss? Modern CPUs use pipelining which executes many instructions parallel. This only works well if everything goes as predicted. If you have an algorithm which works contrary to what the branch prediction thinks and a cache which does not hold the data you need, your performance goes down the drain. Those MIPS mean nothing if not put into the right context.
      - Dylan16807 10y ago
        You can do a lot to work around branches. Cache misses make CPU speed irrelevant, but when you look at your memory system it's another instance of the same problem with the same tradeoffs of frequency vs. work per cycle. And when the "right context" is waiting for the outside world, that's not the most important context.
disposablezero 10y ago
Frequency tends to be somewhat orthogonal to instructions per watt. (It's easish to build hyperpipelined CPUs which have horrendous pipeline stall latency characteristics.) And CMOS tends to dissipate power (most as heat) proportional to the square of the frequency because zero crossing in CMOS logic is a virtual short-circuit. MIPS (the former Hennessy shop), SPARC and other RISC shops tended to ignore more/less the retail consumerization of the CISC MHz wars to bet on architecture fundamentals. I highly recommend taking a digital logic and computer architecture class in a CS program to understand how pipelines/instruction units are laid out (microcoding, branch prediction, pipeline stalls, macro ISA, etc.), what makes them fast/slow and challenges to implementation.
- wyager 10y ago
  One thing that surprised me while taking a processor design course is that pipelining is actually old technology; modern processors are essentially partially nonlinear graph-reduction machines. Your average CPU core might have 6-10 different logic units (multiple ALUs, FPUs, MUs, etc.) possibly shared across 2 "hyperthreaded" virtual cores. This means that if the incoming assembly code is fairly linear (or has no mispredicted branches) and has some partially independent computation, you could feasibly sustain 5+ full instructions per cycle. As a side note, the Tomasulo algorithm is a huge pain in the ass to do in hardware. Props to the processor engineers who are implementing modern OOO execution hardware in whatever awful proprietary HDL/IDE combo your company makes you use.
  - dom0 10y ago
    Oh yes they do. A really excellent example here are ARX (add rotate xor) algorithms in cryptography. Take BLAKE2 for example; the reference C code, compiled to plain x86-64 assembly mainly consists of long rows of addq/xorq/rorq instructions. A modern CPU manages to schedule these so efficiently that the performance difference to a hand-coded SSE or AVX version practically never matters. If you take a peek at Haswell's port map (eg. http://images.anandtech.com/reviews/cpu/intel/Haswell/Architecture/haswellexec.png http://images.anandtech.com/reviews/cpu/intel/Haswell/Archit... ) you'll see that there are four out of eight ports who can do integer arx operations. Since memory and addr ops got their own ports this means that even the straight addq/xorq/rorq code can almost fully utilize the core. This is no accident, though, the algorithm was designed to take advantage of designs like this :)