3 ms·
A balance needs to be striken between the consumers of data (OOO execution, multiple issues, HT threads and multiple cores), and the providers of data, the cach
by minipci1321 10y ago
A balance needs to be striken between the consumers of data (OOO execution, multiple issues, HT threads and multiple cores), and the providers of data, the cache subsystem (and memory etc).
Bigger caches that would be required by more cores in order to keep the "usefulness" of the design in balance, would lead to higher power consumption, which a) is a primary criterium of evaluation of the product such as laptops, even before the computing power; b) not justified given typical "office+home" workload, as already mentioned in the answers.
- amelius 10y agoAlso could it be that bigger caches would require more coherence-logic (or even a more complicated/congested cache-bus), making everything slower, and eventually negating the advantage of more cores?
- imtringued 10y agoYou can make cache coherence scale to multiple cores with precise tracking and the overhead of precise tracking can be reduced by arranging your cores as clusters. Exact tracking basically requires a bit field with one bit for each core. The problem is with the storage overhead since a 64 core cpu would need 64 bits per cache line. However if you had a 64 core CPU you could partition it into 8 clusters with 8 cores each which means you only need 8 bits per cache line for exact tracking. http://www.cis.upenn.edu/acg/papers/cacm12_why_coherence.pdf http://www.cis.upenn.edu/acg/papers/cacm12_why_coherence.pdf