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Intel Completes $16.7B Altera Deal
- vvanders 11y agoNot sure how they think FPGAs are going to reduce their "cloud workload". FPGAs are pretty power hungry (aside from lattice) and only work well if you have some unique requirements.
- tw04 11y agoTell that to Microsoft. http://www.eetimes.com/document.asp?doc_id=1324372 http://www.eetimes.com/document.asp?doc_id=1324372
- sapek 11y agoMore information here: http://research.microsoft.com/en-us/projects/catapult/ http://research.microsoft.com/en-us/projects/catapult/
- Cieplak 11y agoFPGAs are excellent for parallelizing IO, so if the application involves lots of IO, an FPGA coprocessor will likely reduce power consumption if the CPU delegates IO intensive operations to the FPGA.
- emcq 11y agoNot if you're sitting around waiting for data stored on some DB or distributed file system. FPGAs don't do much to address that. However there are certainly cases where you could design very lean systems where you could win with an FPGA, but my guess is the average developer wont be any better at that than they are on the CPU side developing tight high performance code.
- vvanders 11y agoYup, that's my feeling. We can't even get developers to pay attention to CPU cache lines. I'm very doubtful that your average SW dev could understand how to use FPGAs to their advantage.
- virtuallynathan 11y agoJust speed up the database and filesystem with FPGAs ;)
- nickpsecurity 11y agoBecause they can accelerate arbitrary algorithms anywhere from a percentage to 50x increase often for a fraction of the energy and clock rate? I'd guess more so when sequential part is on top tier CPU and accelerator is on its NOC.
- revelation 11y agoWhere is this magic FPGA that takes an arbitrary algorithm and accelerates it 50x? FPGAs have a nice niche for certain applications, and they deserve more prominence, better tooling and widespread use, but they are not magic.
- alain94040 11y agoFPGAs are usually very good at accelerating one computing algorithm at a time. Not two. Just one. They'll beat processors unless the operations are an obvious fit for processors (for instance, floating point). I/O is actually a bottleneck in FPGAs. In practice, most applications require executing plenty of algorithms one after the other, depending on input data, with a lot of glue in between (I/O). FPGAs are terrible at that.
- koko775 11y ago50x isn't unreasonable if you can parallelize and/or pipeline a rigidly-defined process, cutting out as much memory and cache accesses as possible. With the right programming model, 50x seems very, very reasonable, not even magical. A typical computer does a decently high amount of context-switching and cache-loading.
- revelation 11y agoYes, of course. Hence why FPGAs are brilliant for stuff like networking equipment, massively parallel coupled with massive low-level IO. But it doesn't work that way for arbitrary algorithms.
- koko775 11y ago
- petke 11y agoFast cores take exponentially more energy than slow ones. So the solution is to use more slow and simple cores instead. We get more performance per watt that way. On PCs we can use GPU's to make computations in parallel. I guess this is like that, but for servers.
- PascLeRasc 11y ago>Fast cores take exponentially more energy than slow ones What's your source for this/why does this happen?
- wolf550e 11y agoIt is very well known that the out of order execution engine of modern cpu cores has a very high power overhead. https://en.wikipedia.org/wiki/Out-of-order_execution https://en.wikipedia.org/wiki/Out-of-order_execution https://en.wikipedia.org/wiki/Bonnell_%28microarchitecture%29 https://en.wikipedia.org/wiki/Bonnell_%28microarchitecture%2...
- cornholio 11y agoBasic logic: as you cram more and more out of order and parallel execution, branch prediction and other advanced techniques in a core, there is a diminishing return. If it weren't, you could create a single core of unlimited computing power.
- petke 11y agoFrom my fuzzy memory: To make a cpu fast you need to shrink them. To the point that the "wires" in the core are so close together that electrons jump from one another. So there is lots of electrical interference. To overcome this voltage needs to be increased. This takes more power and makes the cpu hotter (which requires cooling). But dont take my word for it. I did some quick Googling. Maybe you can find some better source and explanation: https://en.wikipedia.org/wiki/Multi-core_processor#Technical_factors https://en.wikipedia.org/wiki/Multi-core_processor#Technical... "For general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the operating frequency. This is due to three primary factors: - The memory wall; [...] - The ILP wall; [...] - The power wall; the trend of consuming exponentially increasing power with each factorial increase of operating frequency. This increase can be mitigated by "shrinking" the processor by using smaller traces for the same logic. The power wall poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the memory wall and ILP wall."
- Cieplak 11y agoI'm hoping this will lead to improvements in their FPGA development environments.
- 0xcde4c3db 11y agoI'm not holding my breath. Even if they decide to do it, I imagine it would take a solid 5 years to flush all the crap out of the pipeline.
- vt240 11y agoI was thinking the same thing too. I have always had a much easier time working with the Xilinx/Mentor workflows, and I would love to see the competition in that space. But then I remembered the last time I tried to download my copy of Intel C++; over an hour lost in a maze of broken links, ending with having to open three different support cases, and I stopped holding my breath.
- mozumder 11y agoOK now how quickly can FPGAs be adapted to search through Postgres indexes?
- nickpsecurity 11y agoQuickest way is to use what's called a high-level synthesis tool that converts a high-level version of algorithm to hardware language. Synthagate, Handel-C, Catapult-C, Synflow's C-flow, C-to-Silicon... many tools claim to do it. Best to have someone with hardware background help, though.
- petra 11y agoXilinx has started to offer, for free , such high-level language tool , as long as you use their lower end fpga's, for those interested in trying such tool.
- nickpsecurity 11y agoIs it Vivado they're giving away? That would be pretty awesome given even a Spartan6 is quite powerful.
- petra 11y agoYep vivado HLS.
- aheilbut 11y agoNetezza (acquired by IBM) has been doing this for many years.
- electrum 11y agoNetezza, a data warehouse appliance which was built on PostgreSQL, uses FPGAs as the first step to process data as it is read from disk.
- pjc50 11y agoI can't see how it would help - this kind of search involves almost no computation and a lot of memory/disk bandwidth. People need to remember that FPGAs are not a magic bullet, especially not for throughput; they're better used for low-latency hardware interaction and things where you need cycle-deterministic behaviour. Crypto is a far more interesting potential case.
- nickpsecurity 11y agoHell yes! Intel chips are about to get exciting again. SGI put FPGA's on nodes connected to its NUMA interconnect with great results. Intel will likely put it on its network on chip with more bandwidth and integration while pushing latency down further. 90's era tools that automatically partitioned an app between a CPU and FPGA can be revived now once Intel knocks out those obstacles that held them back. Combine that with OSS developments by Clifford Wolf and Synflow in synthesis that can be connected to OSS FPGA tools to show even more potential here. Exciting time in HW field.
- emcq 11y agoI'm excited about this too, but the article suggests this is an industry wide thing; IBM is doing this with Xilinx, Qualcomm is experimenting with ARM stuff (not sure how this is different than the Zynq), AMD also with Xilinx. If there is something that works here I'm sure Intel wont be the only game in town.
- iheartmemcache 11y agoEven more exciting is the OmniPath[1] stuff that came out as a result of the Infiniband acquisition. RDMA + Xeon Phi + the insane number of PCI-e lanes[2] available for those new M.2 SSDs which post just absolutely insane numbers[3] all of which are supported by ICC[4] and you've got a really budget-friendly HPC setup. I'm really hoping for IBM's OpenPOWER to gain traction because Intel is poised to capture the mid-market in a dramatic fashion. [1] See: IntelOmniPath-WhitePaper_2015-08-26-Intel-OPA-FINAL.pdf (my copy is paywalled, sorry) [2] http://www.anandtech.com/show/9802/supercomputing-15-intels-knights-landing-xeon-phi-silicon-on-display http://www.anandtech.com/show/9802/supercomputing-15-intels-... [3] http://www.anandtech.com/show/9702/samsung-950-pro-ssd-review-256gb-512gb http://www.anandtech.com/show/9702/samsung-950-pro-ssd-revie... [4] https://software.intel.com/en-us/articles/distributed-memory-coarray-fortran-with-the-intel-fortran-compiler-for-linux-essential https://software.intel.com/en-us/articles/distributed-memory... This is for Fortran, but the same remote Direct-Memory-Access concepts extend over to the new Xeon architecture.
- scurvy 11y ago
- belleandsebasti 11y agoFpgas really only accelerate parallel workloads, sequential computation is done easier and just as good with a CPU. Problem with massive parallelism becomes communication costs and spatial routing. Nothing is free. More excited about commodity chips with 100s of cores. Rather have something that's easier to program with a faster dev cycle if I'm going to tackle parallelism.
- fizixer 11y agoTwo words: - Neuromorphic. - Bye bye Xilinx.
- PeCaN 11y agoPretty sure IBM and AMD are both partnering with Xilinx, they're not going anywhere any time soon. (Plus they also have more enterprise contracts than Altera does.)
- ChuckMcM 11y agoSo I have this vague recollection that Intel had an FPGA division in the early 90's that they spun off. Was that what became Lattice? Sad that the Interwebs get really murky pre 1995
- rgbrenner 11y agoGood memory. It was Intel's Programmable Logic Devices unit. First FPGA in 92, and was sold in 1994 for $50m to Altera[0]. The processors were the FLEXlogic line. They only released a few (looks like 4 total[1]). Here's an announcement for one: https://groups.google.com/forum/#!topic/comp.sys.intel/YBUtOwHXv08 https://groups.google.com/forum/#!topic/comp.sys.intel/YBUtO... 0. http://www.embedded.com/electronics-blogs/max-unleashed-and-unfettered/4439610/How-will-Intel-s-purchase-of-Altera-affect-embedded-space- http://www.embedded.com/electronics-blogs/max-unleashed-and-... 1. http://www.intel-vintage.info/timeline19901995.htm http://www.intel-vintage.info/timeline19901995.htm
- cornholio 11y agoIntel CEO Brian Krzanich: "We will apply Moore's Law to grow today's FPGA business, and we'll invent new products that make amazing experiences of the future possible" PHB, how you've grown !
- comboy 11y agoOTA CPU upgrades? ;)