znwu

6 ms·

31.
by znwu 5y ago
It is a 128bit wide vector design. Which means the wdith of actual vector register is 128bit. The 1024bit figure is due to register grouping of up to 8 vector registers which is mandated in the spec.
32.
by znwu 5y ago
To be fair, I dislike a lot of stuff in RISC-V. But there are just so many who won't even bother to read through the spec and start commenting. I personally considers the complexity of designing a microarchitecture-neutral ISA is bey
33.
by znwu 5y ago
> we get continuing bugs and vulnerabilities as a result Background reading: https://huonw.github.io/blog/2016/04/myths-and-legends-about... If you only want safety , then trapping or not, signalling or
34.
by znwu 5y ago
This is some seriously interesting stuff. But they are demonstrating with 16 cores + 30 GB/s & 128 cores + 190 GB/s. And to my understanding they did not really mention what type of computational load did they perform. So this
35.
by znwu 5y ago
Yeah the marking phase cannot be efficiently vectorized. But I wonder if it can help with compacting/copying phase. Also for me the process sounds oddly familiar to vmem table walking. There is currently a RISC-V J extension drafting g
36.
by znwu 5y ago
I'm thinking with that much bandwidth, maybe they will roll out SVE2 with vlen=512/1024 for future M series. AVX512 suffers from bandwidth on desktop. But now the bandwidth is just huge and SVE2 is naturally scalable. Sounds like
37.
by znwu 5y ago
Not sure if it will be available, but 400GB/s is way too much for 8 cores to take up. You would need some sort of avx512 to hog up that much bandwidth. Moreover, it's not clear how much of a bandwidth/width does M1 max CPU in
38.
by znwu 5y ago
Interesing article. Would be great if use better visualization techniques and clear up the sections. It seems that Flutter Desktop performs as expected. Though I would say the margin is not as large as I personally expect, in terms of FPS a