To be fair, I dislike a lot of stuff in RISC-V. But there are just so many who won't even bother to read through the spec and start commenting. I personally co

To be fair, I dislike a lot of stuff in RISC-V. But there are just so many who won't even bother to read through the spec and start commenting. I personally considers the complexity of designing a microarchitecture-neutral ISA is beyond comprehension of any single human being. You could be a legendary* microarchitecture designer / compiler developer / application developer, but no one can be all at the same time. * By legendary I mean across multiple domains, from low-power to high-power to server, from OS to CRUD to HPC. So those kind of one-liner dismissal is really pale when RISCV spec is full of design rationales. IMO, it should at least include both: 1. Show that the rationale does not exist in spec / rationale is wrong 2. Show that your counter-point is significant enough (used widely and cause a bottleneck) Otherwise it becomes a joke for those: 1. who complain code size 2. who think add is better than addi for no-op 3. who is the author of an arbitray-precision numerical library and claims RISCV is shit.