xw3089

5 ms·

1. 1.▲
   by xw3089 3y ago

   There are tons of other practical problems. The HLS generated verilog is name mangled. This makes it really hard to generate all the various control files you need to run the EDA flow, the software that assists in turning verilog into man
2. 2.▲
   by xw3089 3y ago

   I think this comes from the idea that running the EDA flow is like compiling software and that’s the problem, it’s not. The EDA flow, the software that goes from verilog to manufacturable files, is electrical engineering. Sure, it’s heavil
3. 3.▲
   by xw3089 3y ago

   You’re preaching to the choir on improving validation. Like you mentioned, In commercial designs that’s where a majority of the man hours actually go, and coincidentally where basically none go in academia where chisel is popular. I will me
4. 4.▲
   by xw3089 3y ago

   Maybe not no one https://berkeley.municipal.codes/BMC/12.90.050
5. 5.▲
   by xw3089 3y ago

   Yes, that happened to my car. But one could still drive their car after the failure and there was a free recall. https://www.tesla.com/support/8gb-emmc-recall-frequently-ask...
6. 6.▲
   by xw3089 3y ago

   Genuinely curious, what’s the argument for locking down the FPGA?