wren6991

8 ms·

151.
by wren6991 5mo ago
You're right, that was a knee-jerk reaction. Sorry, I take it back.
152.
by wren6991 5mo ago
To support ? Oof.
153.
by wren6991 5mo ago
Not even close. "I made this DSP task faster by focusing on exactly one compute graph on one machine instead of a compute graph compiler that runs on every possible machine" is a real engineering approach, and the AI usage is inci
154.
by wren6991 6mo ago
Yes I agree, something like vi or GNU nano is a great example of a TUI. The meaning is drifting a bit but I think the distinction is useful: a CLI program is one that you can invoke from a Makefile.
155.
by wren6991 6mo ago
CLI is "run a command, get output, drop you back at your shell prompt". TUI is a full-screen interface inside the terminal which you stay inside of, no longer interacting with your shell.
156.
by wren6991 6mo ago
99% of LLM-adjacent software is webslop in a state of perpetually broken churn. OpenCode for example has not yet figured out "maintain a log of all messages and send that log to the SSE endpoint in the same order to get the next respon
157.
by wren6991 6mo ago
> There was no ill intent by evil corporation I simply do not believe you
158.
by wren6991 6mo ago
One of two cases: pushing Verilog through yosys-smtbmc to check design assertions/properties, or writing a lil Python model of some optimisation trick and checking it's equivalent to a more direct implementation. For the former it
159.
by wren6991 6mo ago
Z3 struggles with larger problems. CVC5 or Bitwuzla do a lot better once you get into anything complex. If you're familiar with the Z3 Python API, you'll find the CVC5 one familiar. Caveat: I mostly do logic design, maybe there ar
160.
by wren6991 6mo ago
You need to distinguish safety properties from liveness properties.
161.
by wren6991 6mo ago
Brought to you by classics like "how do I join all of these pthreads that I've detached?"
162.
by wren6991 6mo ago
> I decided to go against the grain of the near-universal advice to "learn to read by reading". ...Why? That advice is universal for a reason. The side adventure with Claude Code strikes me as a distraction from the fact that t
163.
by wren6991 6mo ago
On M5 Pro/Max the memory is actually just attached straight to the GPU die. CPU accesses memory through the die-to-die bridge. I don't see the difference between that and a pure GPU from a memory connectivity point of view. Wrt in
164.
by wren6991 6mo ago
Yeah, it feels intuitively like it should work, but even with full 64-bit modular multiply the bounds don't overlap. I should probably delete that sentence, but on the other hand maybe the wild goose chase will lead to someone finding
165.
by wren6991 7mo ago
Please put the connector on the top of GND. GND goes on the bottom of a schematic.
166.
by wren6991 7mo ago
> MCU cores don't though v6-M doesn't (e.g. Cortex-M0+). v7-M and v8-M do allow unaligned access on Normal memory but not on Device memory.
167.
by wren6991 7mo ago
Yep, RISC-V also has these megapages. 4k is the last-level page size. You get larger pages (4M on 32-bit and 2M/1G on 64-bit) by terminating the walk at higher levels of the page table.
168.
by wren6991 7mo ago
This extension wasn't strictly necessary but it makes decode of Arm instructions faster in the bootrom's Arm emulator.
169.
by wren6991 1y ago
ELF patching is a last resort! We do have some really awful Python ELF patching in the RP2350 ROM build to implement a missing relocation for 16-bit pointers in `movw` instructions, which also saves a ton of space.
170.
by wren6991 1y ago
...although you could certainly implement a Jazelle-style "branch to x86" instruction if you really wanted. It's fine as long as you come up in RVI mode. Unfortunately you would not be able to repurpose the LSB of jalr target
171.
by wren6991 1y ago
RISC-V code density is pretty good these days with Zcmp (push, pop, compressed double move) and Zcb (compressed mul, sign/zero-extend, byte load/store). There is also Zcmt but it's kind of cursed. Hopefully density will keep
172.
by wren6991 1y ago
You still have the overhead of a function call. If you just use / % operators then you'll get a call inserted to the libgcc or compiler-rt routine if you don't have the M extension, and those routines are div or mod only. Usi
173.
by wren6991 1y ago
> publish properly what will end up "standard instruction fusion patterns" (like the div/rem one). The div/rem one is odd because I saw it suggested in the ISA manual, but I have yet to ever see that pattern crop up i
174.
by wren6991 1y ago
I feel like the author might be slightly missing the point here: > The whole premise of fusion is predicated on the idea that it is valid for a core to transform code similar to the branchy code on the left into code similar to the branc
175.
by wren6991 1y ago
Surprised an article published on September 28, 2025 does not include any mention of the P (packed integer SIMD) extension. P adds instructions like integer multiply-accumulate, which have a third register read (for rd). So, they're ta
176.
by wren6991 1y ago
> It must be noted that customer safety and EMC requirements for the mini PC, a standalone electrical item, differ from those for hardware components (such as the PSU) designed to be inside a PC case. The safety standard suggests that ve
177.
by wren6991 1y ago
It's a numbers game. Sentence complexity within a given novel follows a distribution, and if you keep reading then you'll keep getting some input that is at exactly the right level for you to grow. It's normal to stumble on
178.
by wren6991 2y ago
I like this syntax. It's like saying "give me all the members of this object". Kind of like using full-slice [:] in Python to copy a list's values instead of passing by reference.
179.
by wren6991 2y ago
> We just saw big win of ARM over Intel's multi-decade scam We also just saw Arm sue one of their customers following an acquisition of another of Arm's customers, and try to make them destroy IP that was covered by both custom
180.
by wren6991 2y ago
RP2350 maps RISC-V M/U modes onto AHB protection attributes equivalent to the v8-M combinations Secure + Privileged and Non-secure + User. The system-level TrustZone-M filters apply to both architectures, since they're simple bus

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