wren6991

18 ms·

181.
by wren6991 2y ago
If the RISC-V cores were removed, the bit assignment for the critical OTP flags would be different. Quite likely this attack would then have directly enabled Secure debug access to the Arm cores. Whoever wrote that headline lacked even a cu
182.
by wren6991 2y ago
One that bit me was the change to StopIteration propagating through chained generators, following PEP 479. Nothing huge, but I had to patch some previously working code to accommodate the new language release.
183.
by wren6991 2y ago
Someone needs to set up a Clockwork Orange-style viewing session with the Python developers and Linus' WE DO NOT BREAK USER SPACE email: https://linuxreviews.org/WE_DO_NOT_BREAK_USERSPACE I help maintain a small Python
184.
by wren6991 2y ago
RV64 has some reserved encoding space in satp.mode so there's an obvious path to expanding the number of page table formats at a later time. Just requires everyone to agree on the direction (common issue with RISC-V). For RV32 I think
185.
by wren6991 2y ago
> This means that practically only the untranslated bits of the address can be used by the set selection portion of the cache lookup It's true that this makes things difficult, but Arm have been shipping D caches with way size >
186.
by wren6991 2y ago
> I was under the impression from "I'm of the opinion that the lack of arm-like -mcpu=<core>+<optional stuff>+no<disabled stuff> equivalent for RISC-V is a good thing" in the linked discussion that a new
187.
by wren6991 2y ago
Yosys supports very basic SVA (immediate assert/assume, $past etc) in addition to Verilog 2005
188.
by wren6991 2y ago
Double pumping loses its one-cycle latency when you forward to an operation that is genuinely 512 bits wide, like a shuffle. At that point you have to wait for both halves to be available before dispatching. That's another advantage to