wren6991

6 ms·

31.
by wren6991 2mo ago
> Why It Matters Thanks Claude, the analysis looks to be load-bearing, and dare I say the gun may be smoking. This sharpens the framing considerably. Honest caveat: most AI providers' privacy policies have an explicit carve-out for
32.
by wren6991 2mo ago
> C -> "ZcfZcdZca" just by itself is insanity Separating the float load/stores from the rest of the compressed ISA is insanity? Why? > Now I can't make vendor-independent RISC-V code I think this is what RVA23 i
33.
by wren6991 2mo ago
It originally had a range of 4 MiB, and they extended it to 16 MiB in a later ISA revision. The bits with the XORs were originally constant-1 and they wanted to keep backward compatibility, so bits J1 and J2 are interpreted as "if this
34.
by wren6991 2mo ago
> If one of your vendor blobs was specified for the old system and the new system is "similar", you'll just link it in and see what happens. And what if that blob has instructions your new core just doesn't implement?
35.
by wren6991 2mo ago
Fair enough. It's a performance issue but not a functional correctness issue. > Because I think there's a csr to read it the fpu is dirty but... That requires csr extension Yes, and they already unconditionally read that CSR :-
36.
by wren6991 2mo ago
Yeah, this is a bug. They should only be saving the FP state if it's dirty. Also this is one of the reasons I think Zfinx is a better option for embedded (i.e., the standard FP instructions operate on x registers instead of f registers
37.
by wren6991 2mo ago
This is a good point, and of course this is why IP lawyers are so important: they protect you from other IP lawyers.
38.
by wren6991 2mo ago
The arguments were against ISA-level fusion, since they can be fused in the uarch. See for example: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/Archive/EE...
39.
by wren6991 2mo ago
> The fact that the relevant CPU features can’t even be enumerated in user mode just makes it worse. User-mode feature detection is usually used to select paths for acceleration instructions, like SIMD or crypto. The overlapping RISC-V
40.
by wren6991 2mo ago
Yes, I'm serious. I think the overlap is an aesthetic problem rather than a practical one, given that: * The profile used by "Big SoCs" already explicitly depends on F + D + C, implying ZcdZcf, so the newer Zce won't be
41.
by wren6991 2mo ago
When I looked into mconfigptr some years ago I thought it looked like a swirling vortex of pain that might produce something useful some day. Good to see it's still being worked on. Sad to hear ASN.1 is still involved. I added an &quot
42.
by wren6991 2mo ago
They actually did do that. C was split into ZcfZcdZca, so you can choose a non-overlapping subset. It doesn't affect an RV32 non-F core anyway.
43.
by wren6991 2mo ago
The RISC-V fusion arguments from back in ~2018 didn't really pan out. A lot of those fusion opportunities are just instructions now. slli + add? Zba (sh*add). slli + srli? Zbb (zext.*). slli + srai? Believe it or not, also Zbb (sext.*)
44.
by wren6991 2mo ago
You might find this relevant: RISC-V Genealogy (2016) https://riscv.org/wp-content/uploads/2025/02/EECS-2016-6.pdf Or in poster form: https://riscv.org/wp-content/uploads/2025&#
45.
by wren6991 2mo ago
RISC-V is... fine. It satisfies my two requirements for an ISA as a hobby CPU designer, which are: 1. Supported in mainline LLVM and GCC. 2. I can implement it without lawyers sending me a love letter. Everything else, I can fix in post. Th
46.
by wren6991 2mo ago
It's also quite hard to separate Mythos the model from Mythos the campaign (aka Glasswing). They put an enormous amount of compute into bug hunting, and they found some bugs. Fair enough. For me that begs the question: what if they had
47.
by wren6991 2mo ago
The thing that blows me away is it does this at one quarter the total parameter count of K3 (and 40% active parameter count). There's plenty of room at the bottom. > How are you all toying with running this kind of thing in a mega q
48.
by wren6991 2mo ago
We have a first-party figure from the system card [1]: > Mythos 5 reproduced 83.8% of targeted vulnerabilities on a single try, and produced at least one crash in 99.4% of tasks. This is comparable to Claude Mythos Preview, which reprodu
49.
by wren6991 2mo ago
People have had surprising success adding vision to open-weight LLMs that ship without it, like DSV4 Flash [1] or GLM-5.2 [2]. Given this model is already vision-trained I expect that approach will work well here. [1] https://old
50.
by wren6991 2mo ago
I imagine there would also be some cache pressure increase if you inflated all of those ints to 64 bits.
51.
by wren6991 2mo ago
> I wonder if open models are going to start doing that too Yes, some of them do do that. For example Moonshot tried to reward shorter reasoning traces in between Kimi-K2.6 and Kimi-K2.7 Code, and the latter has a mild caveman accent in
52.
by wren6991 2mo ago
> The CoT might "in English", but is it really Yes, it really is. It's emitting literal English text in patterns that have been coaxed through RL into doing some kind of useful fuzzy computation. > is the CoT just anoth
53.
by wren6991 2mo ago
Except for the basic integer types. Change those as much as possible. Hell, CHAR_BIT=12 just to keep them on their toes. Personal pet theory: C is portable as in "you can retarget the compiler to any machine" moreso than "you
54.
by wren6991 2mo ago
> The problem is that these instructions are not applied after the model has finished doing the work, it becomes part of the same work - If you tell an agent to use short sentences, avoid jargon, never overwhelm you and only include the
55.
by wren6991 2mo ago
> Everything being static inline makes it hostile to these older systems which have limited RAM If you don't define `PICOPHYSICS_IMPLEMENTATION` then you just get prototypes and a few struct definitions. From what I could tell the s
56.
by wren6991 2mo ago
I'm fine with a 1k-line function if you just have that many things to do in a row without taking a breath. Breaking it up into smaller functions feels neater when you write it, but when I read it I'm essentially just macro-expandi
57.
by wren6991 2mo ago
Sorry if the joke didn't land; I have heard a lot of different numbers for the size of US labs' models, but never seen any of them substantiated, so I think you're likely to just get more rumours in answer to this question. M
58.
by wren6991 2mo ago
In this situation it's completely moral to go pirate the games on a different platform. Illegal, but moral
59.
by wren6991 2mo ago
I'll ask my uncle (he works for Nintendo) and get back to you on that one
60.
by wren6991 2mo ago
Kimi-K3: 2.8T Qwen3.8-Max: 2.4T DeepSeek V4 Pro: 1.6T DeepSeek V4 Flash: 284B (all are total parameter counts, not active parameters)

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