Fair enough. It's a performance issue but not a functional correctness issue. > Because I think there's a csr to read it the fpu is dirty but... That requires

Fair enough. It's a performance issue but not a functional correctness issue. > Because I think there's a csr to read it the fpu is dirty but... That requires csr extension Yes, and they already unconditionally read that CSR :-) The "CSR extension" is an almost 100% theoretical concern. It was the spec authors being defensive in case the privileged ISA was so flawed they had to throw it out in future, while keeping the base ISA. I don't see that happening at this point. The only exception is deeply embedded cores that drop even basic IRQ and exception support. These are always going to exist and I think they're a sufficiently separate class of processor that they don't really factor into the compatibility equation, because such processors usually only run one program in their entire lives.