tverbeure

44 ms·

691.
by tverbeure 6y ago
I wrote about a deep dive blog post about the SweRV EH1 when it was first introduced. Check out the slides in the "Various" section: https://tomverbeure.github.io/2019/03/13/SweRV.html#various It sh
692.
by tverbeure 6y ago
I reverse engineered that one partially as well, and somebody has been able to get to an LED blinky. However, it has the issue that Intel recently took down Quartus 11.0, which is the last version that supports these FPGAs.
693.
by tverbeure 6y ago
I can't let a topic like this pass by without mentioning commercial (often obsolete) FPGA-based products that are repurposed as development boards. They usually offer FPGAs with much higher capacity for rock bottom eBay prices. * Pano
694.
by tverbeure 6y ago
There are more open source RISC-V that I can count on two hands. Off the top of my head: Rocket, Boom, Boom II, VexRiscv, Ri5cy, Ariane, Vectorblox, SERV, Swerv EH1, Swerv EH2, picorv32, ...
695.
by tverbeure 6y ago
I picked it up again! 2 years ago, I was fed and bored with spending my evenings and weekends doing nothing useful, so I built myself an electronics lab and now I’m in there almost every night. The last few weekends I’ve been trying to reve
696.
by tverbeure 6y ago
Prop 13?
697.
by tverbeure 6y ago
Get in touch! One thing that didn’t make it in the blog post was that a strategically soldered wire shortened the JTAG chain to only include the 2 Intel chips and bypass the AHA chips. The power to the AHA chips gets cut off at some point,
698.
by tverbeure 6y ago
Making an ASIC with pedestrian low speed IOs is easy. Making an ASIC with high speed SERDES IOs that are required for PCIe is hard. Also, AHA has a followup product that doubles the performance by dropping 4 ASICs and 1 FPGA on a board inst
699.
by tverbeure 6y ago
According to their press release, it was an Apache plugin. https://www.businesswire.com/news/home/20081008005207/en/Com...
700.
by tverbeure 6y ago
It's too late now since you've already bought one, but right now, it's still a doorstop than can't be used for anything: I haven't even been able to get one of the LEDs blinking, and that's only the Hello World
701.
by tverbeure 6y ago
I handle most of pull requests and issue tracking on the chubby75 project: it's a great FPGA board for experimenting, but only if you need to drive a lot of IOs and don't have any GPIO input requirements. A replacement for the gen
702.
by tverbeure 6y ago
For those who are interested in submitting airplane data to the non-commercial ADSB-Exchange project, here are my extensive installation instructions: https://tomverbeure.github.io/2019/05/11/ADSB-Exchange-Fee
703.
by tverbeure 6y ago
I'm using SpinalHDL for all my hobby projects, and I use Intel Quartus, Xilinx ISE, or Yosys, depending on the FPGA family. This project is an FPGA based ray-tracer that uses Xilinx ISE written in SpinalHDL: https://github.c
704.
by tverbeure 6y ago
I’ve clocked a VexRiscv at 80 MHz on a very old Cyclone II. On a modern FPGA, 300 to 400MHz should be possible, depending on configuration: caches and branch predictors tends to reduce the clock speed. You can find some results here: https
705.
by tverbeure 6y ago
In a way, the VexRiscv is already implemented in both directions: While stages are specified individually, you can declare those stages to collapse together. The VexRiscv can be specified to be between 2 and 5 stages. In terms of readabilit
706.
by tverbeure 6y ago
If you're happy that it fits in a 35T, you'll be ecstatic to learn that a single VexRiscv fits comfortably in a Cyclone II EP2C5 FPGA. :-) It's hard to find an FPGA that's too small to fit one.
707.
by tverbeure 6y ago
1. Most higher capacity FPGA have a features called "partial reconfiguration" where you can reload a part of the FPGA with a new bitstream. This new part can usually come from anywhere (PCIe, SPI, ...) 2. RISC-V is a ISA. It'
708.
by tverbeure 6y ago
One of the most interesting aspects of the VexRiscv is the way it's implemented. The VexRiscv is written with SpinalHDL, a hardware description library in Scala. But that's not the main thing: in additional to Verilog and VHDL, th
709.
by tverbeure 6y ago
In Belgium, they used the "Claeys formula" for many cases: https://en.wikipedia.org/wiki/Claeys_Formula . (I believe they use something different now, but it's hard to imagine that unions would have allow
710.
by tverbeure 6y ago
I have a very easy solution to this: I don't have a trackers on my blog, so I remain blissfully unaware.
711.
by tverbeure 7y ago
Back in 1995, my buddy and I were on our post-graduation Great America National Parks trip (17 of them, and 7000 miles of driving, in 3 weeks.) We sent a whole bunch of postcards to the home front in Belgium. One of them was sent to a frien
712.
by tverbeure 7y ago
> 4096x3084 Is that a typo? If not: I'm intrigued! Which monitor is it?
713.
by tverbeure 7y ago
When you consider the compression algorithm itself a form of information, your point about it not being quite lossless could be applied to any lossless compression method.
714.
by tverbeure 7y ago
Two things have helped me with that: * I started blogging about my projects. And I try to keep a pace of roughly 1 blog post every 2 months. * I have a mix of on-going long term and short term projects. (I've also submitted talk propo
715.
by tverbeure 7y ago
I honestly don’t see why or how? It’s a synthesis tool. RTL goes in, logic elements go out. It doesn’t need a GUI just like Synopsys DC doesn’t need a GUI. If an IDE for RTL design is your thing, you use a generic tool that may or may not h
716.
by tverbeure 7y ago
That’s a Verilog IDE that can be used with any backend tool...
717.
by tverbeure 7y ago
Is that an apples to apples experience comparison? I use Quartus primarily in a Makefile, just the way I use Yosys and Nextpnr in a Makefile. There really isn’t a whole lot of first order difference. But with Quartus, you get better languag
718.
by tverbeure 7y ago
How many of those processors are used to compile code? The complaint above is about that. Running compiled Rust code on a tiny embedded microcontroller is not a problem. https://medium.com/coinmonks/coding-the-stm32-blu
719.
by tverbeure 7y ago
My money is on breaking it up and sell it for components. The 256 GB in server grade RAM alone cost a fortune.
720.
by tverbeure 7y ago
That doesn't seem like a valid analogy unless an S-class Benz is 10x cheaper than the Elantra?

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