I’ve clocked a VexRiscv at 80 MHz on a very old Cyclone II. On a modern FPGA, 300 to 400MHz should be possible, depending on configuration: caches and branch p

I’ve clocked a VexRiscv at 80 MHz on a very old Cyclone II. On a modern FPGA, 300 to 400MHz should be possible, depending on configuration: caches and branch predictors tends to reduce the clock speed. You can find some results here: https://github.com/SpinalHDL/VexRiscv#area-usage-and-maximal-frequency https://github.com/SpinalHDL/VexRiscv#area-usage-and-maximal... None of those numbers are for the fastest FPGAs.