trsohmers

12 ms·

91.
by trsohmers 9y ago
In all of those cases there was legislation passed after the crises... in this case, the US government has already guaranteed all of the loans and has no way of getting out of the without the US government defaulting. That only leaves room
92.
by trsohmers 9y ago
Most of the student loan debt is owed to private creditors and it is the federal government that insures these loans. If a student doesn't make payments, the lender gets a guaranteed bailout by the government (no need for congress to s
93.
by trsohmers 9y ago
I have been skeptical of the real "value" of cryptocurrencies (outside the technical ability to allow for value transfer, which does not necessitate the coins having value inthemselves), but assuming this is true I have a lot less
94.
by trsohmers 9y ago
The Titan and Tesla NVIDIA cards are still built with 64 bit/double precision in mind with "only" a 50% performance reduction compared to FP32 in most of those devices. It is the GeForce gaming cards and the ones being target
95.
by trsohmers 9y ago
There has been a lot of talk about lower precision and approximate computing over the past couple of years, which I hope will be recognized as a fad with John's (and to a lesser extent mine/REX Computing's) work... Why sacrif
96.
by trsohmers 9y ago
"Mr. President, we must not allow a mineshaft gap!"
97.
by trsohmers 9y ago
Founder of REX Computing here, we taped out in July of 2016 and got our silicon brought up and working back in February. I gave a talk at Stanford showing our hardware and a tiny bit of software: https://www.youtube.com/watc
98.
by trsohmers 9y ago
Just wanted to second close to the top that Augie is not only a great lawyer, but a fantastic human being and committed to helping the startup community.
99.
by trsohmers 9y ago
Or the high frequency trader who spends $20,000 on a machine to try to find all of the $20 bills on the ground before someone else does.
100.
by trsohmers 9y ago
I wasn't saying it wa snot a factor, and I totally agree with you, but the inverse square law per its exact definition does not apply here. I think uBeam is another Theranos, but granted at a much smaller scale. Still can't believ
101.
by trsohmers 9y ago
Not to be defending/advocating that uBeam's tech is actually any good, but the inverse square law refers to omnidirectional transmission, while uBeam's claims are related to directional transmission of power.
102.
by trsohmers 9y ago
It is all marketing bullshit at this point. TSMC's 12nm process is a rebranded version of their 16FFC low power flavor, with literally no other changes other than name so that they can market as being smaller than Samsung/Global&#
103.
by trsohmers 9y ago
I definetly think the latter, and I'd ditch my body for a newer one in 30 years if I could. Would be pretty great if a transporter also did "tune up" of all of the frail biological bits as part of the copying process (without
104.
by trsohmers 9y ago
I really don't understand why people get hung up on this (with the assumption of the impossible guarantee that it is 100% safe, or "bullet proof" as you put it). I am perfectly fine with a Prestige/Star Trek transporter,
105.
by trsohmers 9y ago
I feel I have to defend myself here to some extent (being a now former Thiel Fellow), but I can fairly safely say that the ~20 other Thiel Fellows that I would call "friends" would never do anything close to this at their companie
106.
by trsohmers 9y ago
The assumption by us is that you would be recompiling from at least the LLVM IR level for each different version of the chip. This isn't a real problem for the markets we care about, as they have the source code for all of their applic
107.
by trsohmers 9y ago
It isn't something we have been looking at, as our current customers and target applications would have our chip as a standalone embedded processor. We are working on a prototype PCIe card with an FPGA to be able to convert our SerDes
108.
by trsohmers 9y ago
LLVM is much more compartimentalized, so we can make changes to the backend without touching/breaking other parts. The GCC loader was miles ahead of the LLVM loader up until the past few releases, and we were originally using a modifie
109.
by trsohmers 9y ago
We have played around with having "hints" in the original source code that will be preserved through the IR, but the vast majority of the optimizations and scheduling decisions we need to do are happening once it has been converte
110.
by trsohmers 9y ago
The two best application cases of instruction level parallelism that we have at the moment are our FFT and DGEMM, where our 64 bit instruction word contains the operations for doing a double precision fused multiply add, two 128 bit load&#x
111.
by trsohmers 9y ago
LLVM is the godsend that any new architecture (especially a VLIW) to compete with Intel needed. I'm the founder of a startup that has made a new VLIW processor with our toolchain built on top of LLVM... We get the front end and all of
112.
by trsohmers 9y ago
Designer of the Neo here, and owner of the California "VLIW" license plate. As you can guess, I am a die hard VLIW advocate, and a strong believer that the original promises of VLIW (Drastically simpler decode logic, implicit inst
113.
by trsohmers 9y ago
Pretty sure he is thinking of Elbrus, but AFAIK nothing actually happened from that being announced back in 2004... Elbrus still exists and is making chips. They were basically the Russian Transmeta.
114.
by trsohmers 9y ago
Hack the Planet!
115.
by trsohmers 10y ago
> "... since FinFET mask costs are 10x what they used to be in bulk CMOS" Not true, it is closer to 2 to 3x, and it is (slowly) getting cheaper. While it will take a long time (~3 years) for 14/16nm FinFET processes to rea
116.
by trsohmers 10y ago
It's a flip chip design, so the heatspreader and thermal paste does not touch the part that you are seeing in these images. The areas that I think you are referring to (the big "blob" areas) are computer place and routed stan
117.
by trsohmers 10y ago
Our current plans are for very simple SIMD modes that reutilize the same hardware to maximize Area and power efficiency. Right now, we can separately load/store the upper half and lower half of a 64 bit register with 32 bits of data, a
118.
by trsohmers 10y ago
On your edit: RISC and VLIW are not mutually exclusive. I would say we are a RISC architecture (Load/store based/everything happens on registers, fixed instruction word size, shallow pipeline) that happens to have a much simpler i
119.
by trsohmers 10y ago
1: Around the 30:40 mark in the video I transition to the live hardware demo, where I learned to never do live demos. While it did not work there in person, I do show pictures from it working earlier in the day along with the results from o
120.
by trsohmers 10y ago
Boy, do I have a new processor architecture for you. For the past 3 years my company (REX Computing), has been working on a new architecture that not only covers both of your points, but removes hardware managed caching entirely and replace

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