thisoneforwork

4 ms·

1. 1.▲
   by thisoneforwork 9y ago

   Would "flushing on ignore" not leave the cache side channel open for many instructions before the abort?
2. 2.▲
   by thisoneforwork 9y ago

   Firstly, thanks for the question. As mentioned, not a CPU designer or trying to teach Intel what to do. More like relying on the hive mind to see if I have the right idea. A second instruction in the pipeline would read from the above menti
3. 3.▲
   by thisoneforwork 9y ago

   Not a CPU designer, but my guess is that they will move the cache management logic from the MMU to the µOP scheduler, which will commit to cache on retirement of the speculatively executed instruction. They would then need to introduce some
4. 4.▲
   by thisoneforwork 9y ago

   As it is sometimes said: Die Möglichkeiten der deutschen Grammatik können einen, wenn man sich drauf, was man ruhig, wenn man möchte, sollte, einlässt, überraschen.
5. 5.▲
   by thisoneforwork 9y ago

   This is not a SKU to play with. If $20/hr is indeed the price (I don't know), this is the hourly cost of a couple of waiters. You get to run SAP on someone's infra and someone to support it.
6. 6.▲
   by thisoneforwork 9y ago

   Disclosure: I work at Microsoft, I have worked for Microsoft before and quit, and come back. I love the company, but I am no zealot (tried to standardize a company on Macs during my six years away, because it made sense). I never worked on
7. 7.▲
   by thisoneforwork 9y ago

   Azure's M128 VM size has 128 vCPUs and 2048GB of memory already.