thierry_src

4 ms·

1. 1.▲
   by thierry_src 1y ago

   One of my worry about the presented ideas, and this is present in RISC-V vector ISA if I'm not mistaken, is that register-size-independent vector instructions have random execution times depending on hardware register width. I remember
2. 2.▲
   by thierry_src 1y ago

   An old attempt to this was SWAR-C, (SIMD within a register - C), that could target Neon, altivec and MMX/SSE. I think SWAR-C nailed the syntax (a vector ?: operator, for example). ( https://aggregate.ece.engr.uky.edu/SWA
3. 3.▲
   by thierry_src 2y ago

   As pointed out: it's done, look for algorithmics over grammar-based compression. Querying and search is one of the operation that is doable on compressed data. See Algorithmics on SLP-compressed strings: A survey (Markus Lohrey) ( http
4. 4.▲
   by thierry_src 2y ago

   I'd say there are some possibilities in compression formats that are transparent to certain operations, that is compressed data you can process as is (without decompressing). For example, look at Algorithmics on SLP-compressed strings:
5. 5.▲
   by thierry_src 3y ago

   A few years ago, before the advent of Copilot (and ChatGPT), I was telling my students their future as programmer was bleak, because most coding is either interfacing stuff, or creating an often incorrect heuristic to solve a single instanc