subbdue

7 ms·

1. 1.▲
   How Intel makes sure the FDIV bug never happens again(chiplog.io)

   3 points by subbdue 1y ago|1 comments
2. 2.▲
   by subbdue 1y ago

   The people and breakthroughs behind Intel’s quiet revolution in formal verification
3. 3.▲
   Origami-Inspired Phased Arrays Are Reshaping the Future of Antennas(viksnewsletter.com)

   124 points by subbdue 2y ago|9 comments
4. 4.▲
   The Graduate School Dilemma(viksnewsletter.com)

   1 points by subbdue 2y ago|0 comments
5. 5.▲
   How automotive radar measures the velocity of objects(viksnewsletter.com)

   95 points by subbdue 2y ago|57 comments
6. 6.▲
   The Future of RF Filter Technology(viksnewsletter.com)

   2 points by subbdue 2y ago|0 comments
7. 7.▲
   by subbdue 7y ago

   By EQ values I assume you're referring to the calibration results. These are typically called Delay Registers . Yes, before signing-off on a system, we carefully look at the calibration result and see if there is enough margin. Now wh
8. 8.▲
   by subbdue 7y ago

   > Wow, the cold/warm soaks sound like they make for a very slow iterative process when it doesn't work on the first try. Do you have several systems soaked at the same time? So if the first you test fails, you can adjust somet
9. 9.▲
   by subbdue 7y ago

   Hello .. I’m the author of this article. Reading all your comments was an absolute blast. Since there is some curiosity around temperature and voltage variation - here are some more details for you folks to geek out on. When you build a sys