seldridge

5 ms·

1.
by seldridge 3y ago
> Could even have a crack at toy HDL in the form of the fixed SystemVerilog with a decent type system solution I proposed above using CIRCT as an IR... This is the exact type of activity that CIRCT is trying to make easier! There are bo
2.
by seldridge 3y ago
Yes. There's two common types of modules with different behavior here: `Module` and `RawModule`. The former has implicit clock and reset ports. The latter has no implicit clock and reset. All design can be done with the latter, jus
3.
by seldridge 6y ago
It gives you a hardware testing environment with system calls for reasonable amounts of wall clock time. If you're simulating actual hardware, e.g., a Verilog description of a RISC-V microprocessor compiled to a cycle-accurate simulati
4.
by seldridge 6y ago
(Sorry! Just saw this!) Polymorphism makes it way easier to build hardware that can handle any possible data type. Things like queues and arbiters beg for type parameters (you should be able to enqueue any data). Without polymorphism you ca
5.
by seldridge 6y ago
The MIPS Open ISA project was actually shut down after only a year. [^1] POWER has technically only been "open" for a little under a year. OpenPOWER was always a thing, but this used to mean that companies could participate in the
6.
by seldridge 6y ago
> These are not programming languages, they are hardware definition languages. There's a subtle point in that Verilog/SystemVerilog and VHDL are also just not powerful languages. While parametric, they lack polymorphism, object
7.
by seldridge 6y ago
There is an open PR adding support for the OpenROAD tools [^1]. So, there should be a flow that uses open source VLSI tools eventually. The Google 130nm library is still filling a huge gap as all the open PDKs up to this point were "fa
8.
by seldridge 6y ago
I'm one of the Chisel devs. My biased view is that iterative development with Chisel, to the point of functional verification, is going to be faster than in a traditional RTL language primarily because you have a robust unit testing fr
9.
by seldridge 7y ago
And if this is interesting, Tom gave a great talk at the 2018 Chisel Community Conference on his experiences at that time: https://youtu.be/x_fzoxGpZ_g
10.
by seldridge 7y ago
Thanks for your question. There are some different design decisions between Chisel and Clash (and one or the other may work better for you!). Chisel is an embedded domain specific language in Scala that uses added hardware primitives to bui
11.
by seldridge 7y ago
For non-BRAM/SRAM primitives that you explicitly want to use, your best bet would be a blackbox. However, for memory, Chisel has built in memory hardware types `Mem` (synchronous write/asynchronous read) and `SyncReadMem` (synchro
12.
by seldridge 7y ago
Thanks for looking into Chisel! Great question! However, this is an incredibly difficult question to answer as it relies on comparing language power. Paul Graham's "Beating the Averages" essay gets into this with the "
13.
by seldridge 7y ago
One of the Chisel/FIRRTL devs here available to answer any questions. tl;dr: Chisel/FIRRTL is trying to be "LLVM for circuits". Concretely, Chisel is a domain specific language for describing hardware in Scala. The Chise
14.
by seldridge 7y ago
Thanks for taking a look at Chisel and FIRRTL! (Coming from a Chisel/FIRRTL dev...) Couple of clarifying comments: CDE[^1] is really a Rocket Chip[^2] specific design decision meant to suit the configuration needs of system-on-chip gen
15.
by seldridge 8y ago
This is a surprisingly difficult concept to express... I've taken a stab at it before on StackOverflow [1]. One angle is that Chisel (or some hardware DSL) gives you the ability to access software engineering constructs that Verilog&#x
16.
by seldridge 8y ago
If you're interested in playing with Chisel, the "Chisel Bootcamp" is now hosted on Binder meaning you can run through a fair amount of learning content in a browser [1,2]. As a longer, elaborating point: Chisel is much close
17.
by seldridge 10y ago
The author doesn't have this correct. Chisel is a domain specific language for hardware written in Scala that emits Verilog in Chisel2 or an intermediate representation of RTL (FRRITL) in Chisel3 which is then compiled in an LLVM-like
18.
by seldridge 10y ago
The really cool thing is that existing implementations of RISC-V microprocessors, like what Berkeley provides, rocket ( https://github.com/ucb-bar/rocket ) and boom ( https://github.com/ucb-bar/riscv-
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1 points by seldridge 12y ago|0 comments