rrss

67 ms·

691.
by rrss 7y ago
> We know because hundreds of people died in the airframe. Since both crashes were caused by malfunctioning software, this doesn't tell you anything about the fundamental soundness of the airframe. > We know the MCAS was a workar
692.
by rrss 7y ago
How do you know the airframe is fundamentally flawed? ("the engines are too big" is not an answer).
693.
by rrss 7y ago
19th century peer review was far more entertaining and public than the current system. Frequently, an article would be published, then various colorful responses would be published tearing apart the article (and not infrequently the charact
694.
by rrss 7y ago
Arguably, everything about a mosfet is a quantum effect. But anyway, undesirable quantum effects have been problematic for almost a decade, and were overcome with a variety of techniques (inc FinFET).
695.
by rrss 7y ago
> Topics like sequential consistency and memory barriers are critical pieces of the puzzle and can't be overlooked if you want to get the best out of your lock-free algorithms. I will cover them all in the next episode. Not every ar
696.
by rrss 7y ago
> would be suprised how hard it is to get funding from them to develop it. That's probably because there has been no evidence that wafer scale integration can actually work.
697.
by rrss 7y ago
Probably Google is still doing that 1 "Cloud TPUv3" = 4 TPUv3 chips.
698.
by rrss 7y ago
Those are all C++11 features, right? So they aren't much of an argument in favor of 14, 17, 20.
699.
by rrss 7y ago
Why performance per dollar over performance per watt? Performance per watt doesn't care where the systems are (on-prem vs cloud) and should track perf/$ (unless perf/$ is mostly determined by subsidies).
700.
by rrss 7y ago
> top-line performance comparisons independent of system size Then do that, just don't do it all in one chart with the systems only specified in the fine print.
701.
by rrss 7y ago
I'm not (currently) objecting to the actual MLPerf results. I'm objecting to the fact that your marketing team (at least, I hope it was your marketing team) chose to represent 5 different GPU systems as the same color and 3 diff
702.
by rrss 7y ago
You mean this speedup? > 1024 TPUs are twice as fast as 480 GPUs Might it be because there are twice as many?
703.
by rrss 7y ago
Have semiconductor companies not been on the new architecture path already? It's not like they've just been doing die shrinks this whole time.
704.
by rrss 7y ago
Thanks, I've seen dawnbench, and it's definitely better than this presentation. Unfortunately, their cost numbers aren't actual cost, as they don't allow using AWS spot instance pricing (which is what fast.ai does). htt
705.
by rrss 7y ago
It's disappointing there is no attempt at normalizing results. It's not perf/$, or perf/W, or perf/chip, or anything that might be useful - it seems to just be perf/(the largest machine google/nvidia could
706.
by rrss 7y ago
Too bad it's been discontinued... https://www.tomshardware.com/news/amd-radeon-vii-end-of-life...
707.
by rrss 7y ago
There's some work on enabling larger stuff to run (slowly) via oversubscription. Maybe pytorch will get this capability eventually. https://developer.download.nvidia.com/video/gputechconf/gtc/...
708.
by rrss 7y ago
I don't agree with basing motivations on the appearance of people's names, but it's almost for surveillance by definition, no? Are there non-surveillance use cases for identifying persons of interest across cameras?
709.
by rrss 7y ago
> AVPDEFWXYZLGBTQ RISC-V, is that you?
710.
by rrss 7y ago
Yep, sorry, meant to put 0.1 ... Thanks!
711.
by rrss 7y ago
Replacing all the IEEE 754 hardware with posits won't fix this, though. If you don't care about performance, then the actual solution has no dependency on hardware: 1. Replace the default format for numbers with a decimal point in
712.
by rrss 7y ago
The proposed format has changed several times since 2015, so not all those threads are discussing the same thing as this one. Posits are Type III Unums IIRC, the original proposal was with Type I Unums. Previous proposals were variable leng
713.
by rrss 7y ago
They got rid of the NUMA domains within a single socket , which already don't exist on Intel CPUs.
714.
by rrss 7y ago
Does Linux perf work on Zen 2?
715.
by rrss 7y ago
This is extremely passive. Cool you think that, but do you want them to do anything about it? Maybe "please align the variable definitions."
716.
by rrss 7y ago
> RX5700 isn't winning because it has new node and stuffing in more transistor Sure, I guess, but it is probably still winning because it is manufactured on a new node - transistor count isn't the only thing that matters. Per
717.
by rrss 7y ago
If that check were not there, would intel for display + nvidia for compute work? Better chance than now.
718.
by rrss 7y ago
https://github.com/swaywm/sway/blob/9670ccee683ab985e89eb043...
719.
by rrss 7y ago
Last I checked, sway detects if nvidia.ko is loaded (even if the nvidia gpu has no display) and errors out with some message to the effect of "f you for buying nvidia."
720.
by rrss 7y ago
Thanks. The bit im not sure about is how to prevent ending up Ina state in the middle of a single instruction if one instruction gets split into multiple uops. Like if one instruction gets split into two uops and the first one completes but

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