riyaneel

4 ms·

1.
by riyaneel 6mo ago
Just having a bad english. But yes, the application logic is where the vulnerability can occur. I am adding support for seccomp-BPF but this is complicated for managed runtimes like Go, JVM, Node, Python.
2.
by riyaneel 6mo ago
Exactly, the application logic is the target. Actually doing seccomp bpf base but for managed bindings (Java, Node, Go, ...) add a lot of complexity....
3.
by riyaneel 6mo ago
Im currently adding doc, but 128b alignas are for the Adjacent Cache Line prefetcher and avoid to silence the MESI protocol
4.
by riyaneel 6mo ago
Fair point on the head cache line. Tachyon's target is cross-language zero-copy IPC, not squeezing the last nanosecond out of a pure C++ ring. Different tradeoff.
5.
by riyaneel 6mo ago
You're right on the MPSC point, the ADR overstates it. Aeron's claim-based approach uses a single fetch_add per producer, no retry loop. The real constraints are bounded message size upfront and a caretaker thread for reclamation,
6.
by riyaneel 6mo ago
Exactly, futexes are only used if the consumer opts-in for the sleep phase. The low-latency hot path uses pure spin mode which completely bypasses kernel and fences.
7.
by riyaneel 6mo ago
Tachyon is lock-free and uses a strict alignment to avoid the MESI protocol, but relies on the environment for isolation. You still need core pinning and CPU isolation for true hardware determinism.
8.
by riyaneel 6mo ago
Fair point. The real difference is the narrower: with a futex the producer can inspect consumer_sleeping directly in shared memory and skip the FUTEX_WAKE entirely if the consumer is still spinning. With eventfd you need a write() regardles
9.
by riyaneel 6mo ago
Would love to hear the feedback
10.
by riyaneel 6mo ago
Thanks!
11.
by riyaneel 6mo ago
eventfd always pays a syscall on both sides (~200-400ns) regardless of load. Tachyon slow path only kick in under genuine starvation: the consumer spins first, then FUTEX_WAIT, and the producer skips FUTEX_WAKE entirely if the consumer stil
12.
by riyaneel 6mo ago
Absolutely not, the code following all Hardware principles (Cache coherence/locality, ...) not software abstraction. That not means the code is for a dedicated hardware but designed for modern CPUs.
13.
by riyaneel 6mo ago
Tail latency p99.9 (122ns) are reported
14.
Show HN: Tachyon: 56 ns zero-copy IPC across Python, Rust, Java(github.com)
2 points by riyaneel 6mo ago|0 comments
15.
Bypassing the kernel for 56ns cross-language IPC(github.com)
83 points by riyaneel 6mo ago|33 comments
16.
by riyaneel 6mo ago
I am the author of this library. The goal was to reach RAM-speed communication between independent processes (C++, Rust, Python, Go, Java, Node.js) without any serialization overhead or kernel involvement on the hot path. I managed to hit a