rachitnigam

6 ms·

1.
Reverse Engineering an ASIC(outercloud.dev)
5 points by rachitnigam 29d ago|0 comments
2.
Defining Safe Hardware Design [pdf](people.csail.mit.edu)
41 points by rachitnigam 8mo ago|5 comments
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Formally Speaking, "Transpiler" Is a Useless Word(people.csail.mit.edu)
5 points by rachitnigam 9mo ago|0 comments
4.
An Introduction to Filament(gabizon103.github.io)
2 points by rachitnigam 2y ago|0 comments
5.
by rachitnigam 3y ago
You can express full CPU designs in Calyx (in fact, we have) because it is a superset of a hardware description language. However, Calyx will probably not provide any substantial benefit in this case because there are not that many opport
6.
by rachitnigam 3y ago
Yeah, we've been able to compile entire neural networks like GoogleNet etc. through Calyx. See: https://calebmkim.github.io/files/pubs/src.pdf HLS-like languages are an input to Calyx. For example, we're
7.
by rachitnigam 3y ago
All of those things. Most HLS tools use the CDFG to generate optimized resource bindings and area-aware optimizations.
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by rachitnigam 3y ago
Author of Calyx here. Good question! Usually, you can use OpenCL based drivers to interface with standard memory interfaces on FPGAs. ASICs require a lot more work by either packaging on the same chip as a processor or building IO interface
9.
by rachitnigam 3y ago
But again, this notion of "outsiders" is very gatekeepy. There have been substaintial successes in using high-level programming models for hardware design. The Google VCU paper explicitly mentions using such tools made them faster
10.
by rachitnigam 3y ago
Odd, it works correctly for me: https://rachit.pl/files/pubs/calyx.pdf What platform/browser has this problem?
11.
by rachitnigam 3y ago
Author of Calyx here. I always find these arguments quite reductive but will nonetheless entertain them. "Developing Hardware is a solved problem" For which audience specifically? Maybe if you consider giant teams at large corps p
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GitHub-Centric Research Management(rachit.pl)
2 points by rachitnigam 3y ago|0 comments
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Transpiler, a Meaningless Word(rachit.pl)
2 points by rachitnigam 3y ago|0 comments
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Tell HN: TheForkJoin, a CS research twitch stream/podcast
7 points by rachitnigam 3y ago|1 comments
15.
by rachitnigam 4y ago
You’re thinking of 6110 (advanced programming languages) not 6120
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Constrain – Interactive figures using declarative constraint solving(github.com)
48 points by rachitnigam 4y ago|11 comments
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Why Study Programming Languages(rachitnigam.com)
2 points by rachitnigam 4y ago|0 comments
18.
Lies Academics Believe(rachitnigam.com)
37 points by rachitnigam 4y ago|20 comments
19.
by rachitnigam 4y ago
Not quite. This also has the type ‘a -> ‘a: def nitpick(x): throw “foo”
20.
The Problem with the Problem [video](youtube.com)
1 points by rachitnigam 5y ago|0 comments
21.
by rachitnigam 5y ago
i have never personally called out anyone anywhere ever
22.
by rachitnigam 5y ago
[OP] Yup, that was the intent. I've seen a lot of academic and industrial hand wringing about not wanting to build a compiler because it's an overkill for the solution only to have the people come back 6 months later having built
23.
by rachitnigam 5y ago
[OP] Ah, I've just seen a bunch of people showcase "amazing new tools" that are just bad compilers in disguise. State of the art Database query optimizers are good examples of this.
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by rachitnigam 5y ago
Racket is often heralded as the "programming language programming language" and comes with tons of features to build full blown languages: https://racket-lang.org/ The most complete language/ecosystem that re
25.
Dear sir, you have built a compiler(rachitnigam.com)
355 points by rachitnigam 5y ago|175 comments
26.
Personal Infrastructure for PhD Students(rachitnigam.com)
2 points by rachitnigam 5y ago|0 comments
27.
Tez Bio – Create a personal page in seconds(tez.bio)
2 points by rachitnigam 5y ago|0 comments
28.
Growing an Open-Source Hardware Infrastructure(calyxir.org)
1 points by rachitnigam 5y ago|0 comments
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Show HN: A parallel snapshot testing framework in Rust(github.com)
4 points by rachitnigam 5y ago|0 comments
30.
From Hardware Description Languages to Accelerator Design Languages(sigarch.org)
3 points by rachitnigam 5y ago|0 comments

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