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prbs23
searching PlanetScale…
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by
prbs23
15d ago
I'm working on building open source control firmware that runs on the Masterbuilt Gravity series electronically controlled charcoal smokers. https://gitlab.com/prbs23/freefall_800 The smoker hardware itself is pre
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prbs23
2y ago
As long as you are using the LoRaWAN protocol (not just LoRa modulation), encryption is not optional. It's built into the link layer of LoRaWAN, and a device cannot join a network without a unique key that's shared out of band. Al
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prbs23
2y ago
Interesting concept for a project... From what I have seen in the industry, it seems like this is something every organization ends up developing at least one custom tool for. EDA vendors even generally sell their own solution to this probl
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prbs23
2y ago
This is an awesome write up! I have one of these scopes, with exactly this issue after a long period in storage. When I was looking into it a few years ago the failure mode was known but I couldn't find a recovery procedure. I'll
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prbs23
3y ago
I don't understand why fuzzing hardware is being presented as a new thing here... In silicon validation, constrained random testing has been the standard methodology for at least 10 years. With the complexity of modern CPUs, it's
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prbs23
3y ago
https://www.prbs23.com/blog/ Started a couple years ago, but I don't have as much time to write as I'd like. The majority of topics relate to ASIC design and verification, since that is my day job, but with s
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Combining Dist Constarints in SystemVerilog
(prbs23.com)
2 points
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prbs23
3y ago
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prbs23
3y ago
I rewrote the UI for an off the shelf WiFi digital photo frame so that it shows the latest raw images sent back from the Perseverance Mars rover. https://prbs23.com/blog/posts/picture-frame-from-mars/ The pic
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prbs23
4y ago
If you are interested in more OSSI varieties like those, check out Wild Garden Seed: https://www.wildgardenseed.com The owner, the Frank Morton who was mentioned in article, is the original breeder of both Gildenstern and Dazzli
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prbs23
4y ago
Most architectures do not provide an interrupt that is generated by an integer overflow. Since this would be a significant architectural change in the hardware, it can't be simply added in. Additionally, if you are running inside an op
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prbs23
4y ago
I somewhat recently blogged about my process of setting up a private LoRaWAN network as well. https://prbs23.com/blog/posts/getting-started-with-a-private... LoRaWAN is definitely an interesting mix of open source
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prbs23
4y ago
As others have said it's not the concept of DWDM that's new here. That has been around for a while. What is interesting here is that they have managed to integrate a DWDM transceiver onto a single silicon-photonic chip. As someone
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prbs23
4y ago
> No. I won’t do that. It inhibits natural communication. Quite the opposite, it inhibits effective communication. Giving someone a one sentence summary of why you need to talk enables them to be prepared for the discussion you want to h
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prbs23
4y ago
From what I have seen of both the open source and commercial EDA software, I think it would take a well funded team somewhere around 4 years of development to catch up with the current state of the art. If we're talking about EDA emula
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prbs23
4y ago
You seem to have already made a judgement about IME and associated management processors by calling them backdoors. Intel doesn't put IME into their processors to be a back door, but to, as the name suggests, manage the processor. The
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prbs23
4y ago
I totally agree that having visual diagrams of a code base can be super helpful, especially when getting familiar with the code, or onboarding a new engineer. However I don't think we see automated tools because generating a useful dia
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prbs23
4y ago
It feels like there is a cultural difference here. If someone tells me something in a one on one or small group conversation, my default assumption is that I should not share that with anyone else. The idea that I would have to tell someone
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prbs23
5y ago
I've been following the IceStorm project for a while and it's some really impressive work. Now if only we could get a decent open source SystemVerilog simulator to go along with it. As someone who works in the ASIC design world, t