phire

47 ms·

631.
by phire 3y ago
They got a tip narrowing her location down to a single city. We don't know where that tip came from, but sounds like she already messed up by reaching out to friends and family, or maybe logging into an old internet account. It was onl
632.
by phire 3y ago
I've seen 2 done after the admin became uncooperative and kind of held the community forum hostage. They even went a step further, deleted all the old posts out of the database and setup a redirect to the new forum hosting. Very illega
633.
by phire 3y ago
Yes, that was the memory glitching attack. But it was a pretty hard exploit to pull off, the required pulse was pretty short and required getting lucky. Nobody ever developed it into something particularly useful for end users, and it didn&
634.
by phire 3y ago
I also worked on PSGroove. Though that was very much a team effort, I knew nothing about USB before working on that. From memory, my contribution was mostly tweaking the code until it worked, I think my PS3 was the first to be exploited by
635.
by phire 3y ago
I think at this point, the chance of Trump not winning the Republican Nomination is basically the chance of him dying before the convention.
636.
by phire 3y ago
> (it also being primarily a vehicle for piracy certainly didn't help). The piracy hacks never used OtherOS. The first piracy hack (the PSJailbreak dongle exploit) simply exploited the GameOS usb stack and wasn't released unt
637.
by phire 3y ago
The stamp doesn't touch the silicon or any other solid material, it hovers just above. It only touches a liquid photo-resist that is spread on the wafer. The stamp is transparent, which allows UV light to shine though and exposes the p
638.
by phire 3y ago
You don't actually need radar to have air traffic control. It's just that ATC can't provide tracking services for the entire route. Instead, aircraft file their routes in advanced (which are either a series waypoints, or a fi
639.
by phire 3y ago
The real std::array is static. But c doesn't really have any way to do static arrays, so c_std has decided to implement a dynamic array with an api similar to the std::array. The documentation is correct regarding what c_std has actual
640.
by phire 3y ago
It was a pretty shitty defence. Facebook were trying to argue that Section 230 somehow gave them immunity from their own terms and conditions.
641.
by phire 3y ago
I really should do a blog. I have plenty of good comments and discussions (like this one) spread randomly throughout hacker news and reddit, that could do with being fleshed out and published. And recently I've been pondering the idea
642.
by phire 3y ago
> Merely pointing out that OoO and register renaming weren't really pioneered in x86 architectures in the late 1990's. As usual, it's an incremental process, with no clear start. Yeah, the incremental nature makes it har
643.
by phire 3y ago
> Footnote: I am convinced that we'll see a fork (of sorts) of RISC-V for the GBOoO segment. Yeah, seems likely. Qualcomm has been trying to push RISC-V to be better for GBOoO after ARM fucked them over with their Nuvia purchase.
644.
by phire 3y ago
> I am under the impression that the design was heavily data driven, building on decades of industry experience in many different sectors and actually providing efficient instructions for the operations that are used the most in real c
645.
by phire 3y ago
I've had "attempt to implement a wide x86 instruction decoder on an FPGA" on my list of potential hobby projects for a long time. Though I was only planning to do the length decoder. My understanding is that length decoding i
646.
by phire 3y ago
> Mitch Alsup calls it GBOoO (Great Big Out-of-Order). I like that term. Do you have any suggested reading material from Alsup? ------------ > I see what you're pointing at. I don't think that we'll fully agree on th
647.
by phire 3y ago
Yeah, I agree that the writing is on the wall for x86. As you said, power consumption does matter for laptops and server farms. I'm a huge fan of aarch64, it's a very well designed ISA. I bought a Mac so I could get my hands of a
648.
by phire 3y ago
> designing MRISC32 have made me appreciate the clever encoding tricks that go into fitting all instructions into 32 bits. Keep in mind that the average RISC ISA uses 5 bit registers IDs and uses three-arg form for most instructions, tha
649.
by phire 3y ago
> I guess it's a debate of nomenclature, which lacks real importance (although it helps to reduce confusion). Agreed. I wouldn't be pedantic about this for a higher level discussion, but when you start to get into the weeds
650.
by phire 3y ago
Yeah, that logic seems to all work out. I found annotated die shots of Zen 3 and Zen 4 that pretty much confirm the op cache: https://locuza.substack.com/p/zen-evolution-a-small-overview Pretty strong evidence that AMD
651.
by phire 3y ago
It's only a load/store architecture if you consider the "unfused-uop" to be the native internal ISA of the underlying pipeline. But that seems to be an incorrect perspective. The pipeline's native internal ISA appea
652.
by phire 3y ago
> I was under the impression that internal instructions followed the load/store principle since I assume that the internal pipeline is a load/store pipeline? Well... peterfirefly is making a very generalised statement that is
653.
by phire 3y ago
According to the label, that block contains both the uop cache AND the microcode ROM (which is actually at least partially RAM to allow for microcode updates). I guess it makes sense to group the two functions together, they are both altern
654.
by phire 3y ago
Well, they only need slightly more range. 300km isn't really enough, but 350km is plenty. From what I can tell, the design is still in development. The 300km number is probably more of a conservative estimate than an actual range. The
655.
by phire 3y ago
Worth keeping in mind that Helen Keller didn't loose her hearing (and sight) until an illness at 19 months old. At this age, a child's brain has already locked in the sounds for their native language and lost the ability to learn
656.
by phire 3y ago
Christchurch to Wellington is a bit of a stretch for the range. It's too far to use the Harbour infrastructure at either end. You would have to build a pier on the southern side of Wellington (say Island Bay) and then use New Brighton
657.
by phire 3y ago
Interesting. The H13 codename suggests it's actually M1 derived. And no sign of the GPU, which goes by the name AGX, seems to be more IPU than anything else.
658.
by phire 3y ago
There is no way Apple designed the R1 from scratch, it will contain a bunch of components from their other SoC designs. Obviously it's going to have quite a few more IPUs than a standard SoC, which only have to handle ~4 cameras. It al
659.
by phire 3y ago
The capacity might be small, but with 256GB/s of bandwidth, that's right up there at modern GPU levels, roughly comparable to a RTX 4060. And that's apparently from single chip, the RTX 4060 needs 6 chips get equivalent bandw
660.
by phire 3y ago
I think it's a bit strong to say that branch prediction "solves" the problem of x86's complex variable length encoding. But it certainly goes a long way to mitigating the handicap, and allowing x86 uarches to be very com

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