miczyg

3 ms·

1. 1.▲
   by miczyg 1y ago

   I did not have any encounters with ES CPUs from AMD. I just remember my experience with Intel ES CPUs, which used a different set of keys for blob signing. I connected the dots and assumed that this is also true for AMD. It is not about the
2. 2.▲
   by miczyg 1y ago

   It is not so easy on servers. The AMD servers platforms perform RAM training on each boot, even before the CPU starts execution the firmware. So no matter of your BIOS/coreboot performance, you have a guaranteed 2min++ boot time (depen
3. 3.▲
   by miczyg 1y ago

   This is the source of only a single application (out of 30 or 40?). :)
4. 4.▲
   by miczyg 1y ago

   > Strange, but it is missing support for 9005 Turin. How can this be (except of 400W+ models)? I'm not a board design specialst, but it is not uncommon that boards get newer revisions to support next gen CPUs with compatible sockets
5. 5.▲
   by miczyg 1y ago

   That's true. The PCIe lanes on EPYC server CPUs are divided into the main Gen5 links on the SERDES (like I explained in the post) and the other lower speed lanes (Gen3/Gen4) come from the Bonus links. It is shown on the figures in