mbitsnbites

14 ms·

91.
by mbitsnbites 4y ago
One of the problems with the decoder is that it's "always on" so it always draws power (unlike the SIMD unit, for instance). I also think that the uop L0 cache is closer to where the L1I cache is in a fixed width RISC impleme
92.
by mbitsnbites 4y ago
I agree, but in absence of an accurate method this felt like the second best method. Then there's also the elephant in the room that I'd like to write an article about some time: The decoder/translator + uop-cache in the fron
93.
by mbitsnbites 4y ago
Will have a look at -O2, time permitting.
94.
by mbitsnbites 4y ago
> I would expect the -O2 numbers to reflect better the actual ISA capabilities. I will have a more thorough look at -O2 too, good point. However w.r.t. "ISA capabilities" the simple fact is that compilers don't use CISC st
95.
by mbitsnbites 4y ago
Simple: Optimizing for small code size is uninteresting for 99% of the software that a CPU runs. What matters is performance (especially when you argue that dense code is good for performance), and most real world software is optimized for
96.
by mbitsnbites 4y ago
Just using I$ hit ratio is problematic in many ways. E.g: - You'll probably not find implementations of different ISAs with identical cache configurations (size, associativity etc). - It says little about what work is actually done (di
97.
Debunking CISC vs. RISC code density(bitsnbites.eu)
69 points by mbitsnbites 4y ago|97 comments
98.
by mbitsnbites 5y ago
My general rule is: Don't abstract something before you have at least two different implementations that serve roughly the same purpose.
99.
by mbitsnbites 5y ago
Alpha (1990s) had something along those lines called PALcode. Also check out the term "millicode" (IBM system/390, also 1990s). It's probably higher level than you are asking for, though. The ISA is actually there as an
100.
Denser machine code than C++ code (compiler optimizations) (2021)(bitsnbites.eu)
1 points by mbitsnbites 5y ago|0 comments
101.
Three Fundamental Flaws of SIMD(bitsnbites.eu)
56 points by mbitsnbites 5y ago|20 comments
102.
MRISC32 – Stabilizing the Base Architecture(bitsnbites.eu)
1 points by mbitsnbites 5y ago|0 comments
103.
by mbitsnbites 8y ago
Update: I just moved the scalar register file to block RAM, and now the pipeline uses ~1800 ALMs, or 9% of the chip logic.
104.
by mbitsnbites 8y ago
I'm still learning FPGA:s myself, so I'm not sure if I can give you a relevant figure. Currently the A1 pipeline (no memory subsystem) synthesises to 2000-3000 ALMs (or about 15% of the logic in the device I'm targeting). Tha
105.
by mbitsnbites 8y ago
Thanks for the reference - I have not heard about the Convex C-Series before so I'll be sure to look it up. While the MRISC32-A1 does serial vector processing, the idea is that you should be able to do parallel processing with the same
106.
by mbitsnbites 8y ago
I suspect that what you say is true. One thing worth considering though is that on x86_64 you actually use the vector register file for floating point (and it can do integer too!). On the MRISC32 you have a vector register file with 32 regi
107.
by mbitsnbites 8y ago
Yes, I've seen it. It's quite neat. On the other hand it seems more complex to implement in hardware. In the simplest possible design, the cost of vector support in the MRISC32 is essentially the cost of the register file (i.e. th
108.
The MRISC32 – A vector first CPU design(bitsnbites.eu)
87 points by mbitsnbites 8y ago|18 comments
109.
by mbitsnbites 9y ago
SSD types: for the machines that are identical, they are the same Linux filesystem: stock ext4
110.
by mbitsnbites 9y ago
That's the easy case. In a typical enterprise environment a software developer may be faced with several roundtrips to the centralized/outsourced it support to get their build folders white listed in the company approved (and forc
111.
by mbitsnbites 9y ago
I didn't think that these benchmarks would get this much attention. I personally made them because I could not believe that identical Windows and Linux machines were performing so different in typical software development tasks (Git, C