leeter

9 ms·

91.
by leeter 4y ago
Sounds like M68K or something similar, although Alpha AXP had similar byte level access issues. A compiler on either of those platforms likely would add a lot of fix up code to deal with the fact they have to load the aligned (either 16bit
92.
by leeter 4y ago
I'm curious how much they'll pull over from the existing DLCs, the Plazas and Promenades pack does allow for pedestrian cities. But not in a European sense despite the dev being in Europe.
93.
by leeter 4y ago
It's not just backwards compat, it's all the crazy guarantees that the stdlib has to make. Most code doesn't have strong exception guarantees... the stdlib generally speaking does. It also has to deal with all sorts of silly
94.
by leeter 4y ago
This was not what I thought it was. I assumed it was the `for(auto f : <collection of class>)` issue that STL tried to fix and gave up on. Turns out it was initializers and locks. Extending them to live as long as the loop much like t
95.
by leeter 4y ago
I keep hoping that the C and C++ committees will get together and standardize some of that in the form of C23/C++11 style attributes. But that is sadly likely a naïve hope.
96.
by leeter 4y ago
Primary ATC is still done that way but at least for the big jets there are other ways they send digital comms to ATC[1]. The main reason is because radios fail and more complex radios fail more easily. A standard Jetliner carries three radi
97.
by leeter 4y ago
RISC Architectures confirmed murdered by Itanium: Alpha AXP, MIPS (on the desktop), and HP PA-RISC Architectures set back significantly by Itanium: POWER, SPARC
98.
by leeter 4y ago
> I'm curious did Itanium fail because the model of pushing the complexity onto the software and a human failed or did it fail because of lack backward compatibility for a world that was largely x86 at that point? The answer is: yes
99.
by leeter 4y ago
To answer the last question first: Yes instruction decoding is dirt cheap (generally speaking) the thing that slows down a CPU is memory model, register retirement etc. In theory RISC was intended to be basically no microcode where the CPU
100.
by leeter 4y ago
The article misses a lot, it assumes the only battleship on battleship combat was Jutland. That's simply not true. Surigao Strait[1] and the Naval Battle of Guadalcanal[2] both definitely occurred. As did Hood/Bismarck (this one d
101.
by leeter 4y ago
Correct, the main value of std::out_ptr is the exception safety. There is no gap between the call and when you wrap the value in a smart pointer where something can happen and cause a leak. Is it strictly necessary in all cases? No, but it&
102.
by leeter 4y ago
It would; you'd just have to supply a custom "free_deleter" in the definition of the unique_ptr that calls free instead of delete. I've used this for Windows System calls like GetAddrInfoExW which requires calling FreeAd
103.
by leeter 4y ago
No idea, my app is open source and I do other things at my day job.
104.
by leeter 4y ago
Even GDI runs on the GPU[1] it just is slower because bitmaps are stored in system ram vs VRAM. IIRC there are tricks a driver can use to make it faster by default[2]. The (admittedly very dumb) issue I as a developer have switching from MF
105.
by leeter 4y ago
My understanding is yes and no. In the pre DX12 era drivers often contained full replacement shaders for games sometimes. Where the OEM would hand write a replacement that worked better than what the game dev did, potentially on a GPU sku l
106.
by leeter 4y ago
If I have to buy something on Amazon I've gone out of my way to make sure I'm buying from them directly lately. Too many issues with them pulling crap like this when it's a third party seller. But by forcing them to be the se
107.
by leeter 4y ago
I think I saw that one; but the one that comes to mind is also: https://www.techdirt.com/2018/04/27/how-microsoft-convinced-...
108.
by leeter 4y ago
I seem to recall someone else getting in trouble for distributing Windows ISOs in the past. MS tends to get very touchy on that ostensibly for security reasons (which I actually get). They seem tend to look askance at scripts that strip dow
109.
by leeter 4y ago
> I suspect it might have been a common idiom in pre-C99 days. There is a Blog from Raymond on this[1]. The TL;DR: is that zero length arrays and FAMs weren't legal until C99. Not sure where the support from MSVC factors in. But th
110.
by leeter 4y ago
I'm mixed on this personally, on one hand... I get it. Having curl on the XYZ micro controller you're using for a project is good. At the same time the only reason MSVC added c99 support was community pressure because major projec
111.
by leeter 4y ago
Short answer: Maybe[1] Longerish answer: Still maybe, drivers are going to be an issue. Just because the thing can boot into a DOS compatible mode doesn't mean it will have windows 9x compatible drivers. Having DOS drivers does not als
112.
by leeter 4y ago
My suspicion is you're right. Mostly based on Raymond's blog on the role of DOS in Windows 95[1]. Where people using weird drivers and other things that got in the way of 32bit disk access could massively slow down the system. It&
113.
by leeter 4y ago
I think to some extent all ISAs that are asked to do performant computing inevitably drift from RISC/CISC into FISC (Fast Instruction Set Computing) in the sense they get instructions that are specifically designed to accelerate the mo
114.
by leeter 4y ago
> If I put in an SSD it might even be faster. I think most of the retro youtubers I've seen have done this mod along with PRam battery replacements that don't leak. They seem to use the m.2 SATA mode drives to 44pin like thus (
115.
by leeter 4y ago
Correct, AFAIK the main reason to not support Win16 protected mode was the size the relevant bits of HANDLEs which would have been severely limited to 16bits. Completely obviating the reason to use 64bit windows. As is HANDLEs are 32bits of
116.
by leeter 4y ago
If the allegation that MS is locked to Qualcomm is true and the support of TSO as mentioned in other comments does not include any offering from the same my guess is MS hasn't bothered. They may yet if Qualcomm implements it.
117.
by leeter 4y ago
I really wish Apple wasn't so secretive, this sort of thing makes an excellent tech talk at conferences.
118.
by leeter 4y ago
Interesting, this is news to me. More curious that A64fx has it since that's an HPC chip. They must have a very valid reason for it (I've definitely run into HPC code that is absolutely garbage and would need it to be stable).
119.
by leeter 4y ago
I think it's important to call out that Rosetta 2 on Apple silicon uses a special mode that changes how the memory model works to support x86 style memory ordering. That massively reduces the amount of work needed to emulate x86 and x8
120.
by leeter 4y ago
The bigger callout is the safety margins that were assigned to each plug. The new connector runs pretty much right at rated margin minus 84W (6pins * 12V * 9.5A = 684W) for losses at full spec. The old connector was rated for 324W (3pins *

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